From db7d68b317b0e7a428ef5698763c848e7ca0e256 Mon Sep 17 00:00:00 2001 From: Fcalva Date: Sat, 7 Sep 2024 18:18:06 +0200 Subject: [PATCH] Update spec.txt --- spec.txt | 660 +++++++++++++++++++++++++++---------------------------- 1 file changed, 328 insertions(+), 332 deletions(-) diff --git a/spec.txt b/spec.txt index 22a1b98..af104f0 100644 --- a/spec.txt +++ b/spec.txt @@ -1,332 +1,328 @@ -instruction format: - big endian - 16bits - -Bit order: -0 : Largest (leftmost), 7 : smallest (rightmost) - - -registers: - r0-r12 (mov 0x0-0xc): - general purpose - 8 bits - r13-r15 (mov 0xd-0xf): - Interrupt reserved - 8 bits - ac,pr (special 0x0,1): - accumulator, progam counter - 16bits - ac0-1,pc0-1 (lds/sts 0x0-1,0x2-3): - accumulator, progam counter - 8-8bits (lower-upper) - id (special 0x2): - interrupt data, - set by the interrupt - if raised by bus - 8bits - in (Special 0x3): - interrupt register, - contains the type of - interrupt - 4bits - bits 0-3 will always be 0 - t bit: - is set by comp ops - 1bit -calling conventions: - r0-r1 : return registers - r2-r11: call args - r12 : stack pos - r13-15:interrupt reserved (only adressable in interrupt mode) - caller pushes desired return addr - to stack, callee jumps to it - -Interrupts: - Hardware interrupts: - 0x0 : Invalid instruction - The 15 other interrupts are free to - define by the user - On interrupt (either called through - the bus or itp) -startup: - the cpu will look - at adress 0x0,and - expects to find : - -0x0-1: adress of - the starting - point,will be - jumped to - -0x2-3: adress of - the stack, the - adress will be - read here - everytime - -0x4-5:adress of - the interrupt - handler, the - adress will be - read here - everytime - When an interrupt is raised, the cpu will allow acces - to r12-15 and push the resume adress to stack (in - order pc0 then pc1) - -instructions : - format: - rm,rn: general purpose registers - #imm:immediate signed 8bit value - *rm:memory at adress (pc+rm) - *#imm:memory at adress (pc+#imm) - sr: pr,ac - sr0-1: pr0-1/ac0-1, in/id - st: stack adress that is at 0x2, - abreviation for explanation only - nop : - 0b0000000000000000 - 0x0000 - No-OP: - Does nothing - 1 clock - mov rm,rn: - 0b00100000mmmmnnnn - 0x20mn - MOVe : - rm <- rn - 1 clock - mov rn,#imm: - 0b1000nnnnmmmmmmmm - 0x8nmm - rn <- #imm - 1 clock - mov rm,*rn: - 0b11000000mmmmnnnn - 0xB0mn - rm <- *(pc+rn) - 1 clock - mov rn,*#imm: - 0b1001nnnnmmmmmmmm - 0x9nmm - rn <- *(pc+#imm) - 1 clock - mov *rm,rn: - 0b11000001mmmmnnnn - 0xB1mn - *(pc+rm) <- rn - 1 clock - mov *#imm,rn: - 0b1010nnnnmmmmmmmm - 0xAnmm - *(pc+#imm) <- rn - 1 clock - mov *rm,*rn: - 0b11000010mmmmnnnn - 0xB2mn - *(pc+rm) <- *(pc+rn) - 1 clock - mmv rm, *sr: - 0b11000011mmmmssss - 0xB3ms - Memory MoVe - rm <- *sr - Meant to be used with the accumulator - 1 clock - mmv *sr, rm: - 0b11000100ssssmmmm - 0xB4sm - *sr <- rm - Meant to be used with the accumulator - 1 clock - psh rm: - 0b11000101mmmm0000 - 0xB5m0 - PuSH to stack: - *(st+r11) <- rm - r11 <- r11+1 - 2 clocks - pop rm: - 0b11000110mmmm0000 - 0xB6m0 - POP from stack - r11 <- r11-1 - rm <- *(st+r11) - 2 clocks - lds sr0-1,rm: - 0b11100000ssssmmmm - 0xE0sm - LoaD Special : - sr0-1 <- rm - nop on pc - 1 clock - sts rm,sr0-1: - 0b11100001mmmmssss - 0xE1ms - STore Special : - rm <- sr0-1 - 1 clock - add rn,rm: - 0b01000000nnnnmmmm - 0x40nm - ADD : - rn <- rn+rm - 1 clock - add r0,#imm: - 0b01001000mmmmmmmm - 0x48mm - r0 <- r0+#imm - 1 clock - sad sr0-1,rm: - 0b11100010ssssmmmm - 0xE2sm - Special ADd - sr0-1 <- sr0-1+rm - (16bit add) - nop on pc - 1 clock - sub rm,rn: - 0b01000001mmmmnnnn - 0x41mn - SUBstract : - rm <- rm-rn - 1 clock - shl rm: - 0b01000010mmmm0000 - 0x42m0 - SHift Left - rm <- rm<<1 - pure shift, no keep sign - 1 clock - shr rm: - 0b01000011mmmm0000 - 0x43m0 - SHift Right - rm <- rm>>1 - pure shift, no keep sign - 1 clock - and rm,rn: - 0b01000100mmmmnnnn - 0x44mn - binary AND : - rm <- rm&rn - 1 clock - or rm,rn: - 0b01000101mmmmnnnn - 0x45mn - binary OR : - rm <- rm|rn - 1 clock - xor rm,rn: - 0b01000110mmmmnnnn - 0x46mn - binary eXclusive OR: - rm <- rm^rn - 1 clock - not rm: - 0b01000111mmmmnnnn - 0x47mn - binary NOT : - rm <- !rm - binary not - 1 clock - rtb : - 0b0110000000000000 - 0x6000 - Reset T Bit : - t <- 0 - 1 clock - gth rm,rn: - 0b01100001mmmmnnnn - 0x61mn - Greater THan : - t <- rm > rn ? 1:0 - 1 clock - gts rm,rn: - 0b01100100mmmmnnn - 0x64mn - Greater Than (Signed): - t <- rm > rn ? 1:0 - (signed) (signed) - 1 clock - eql rm,rn: - 0b01100010mmmmnnnn - 0x62mn - EQuaL : - t <- rm == rn ? 1:0 - 1 clock - stb rm: - 0b01100011mmmm0000 - 0x63m0 - Store T Bit: - rm <- t - 1 clock - br *rm: - 0b10110010mmmm0000 - 0x32m0 - BRanch : - pc <- pc + rm *2 - (signed) - 1 clock - br *#imm: - 0b10110000mmmmmmmm - 0x30mm - pc <- pc + #imm*2 - 1 clock - bt *rm: - 0b10110101mmmm0000 - 0x35m0 - Branch if True: - If t == 1, - pc <- pc + rm *2 - (signed) - else is nop - 1 clock - bt *#imm: - 0b10110001mmmmmmmm - 0x31mm - If t == 1, - pc <- pc + #imm*2 - else is nop - 1 clock - bf *rm: - 0b10110011mmmm0000 - 0x33m0 - Branch if False: - If t == 0, - pc <- pc + rm *2 - (signed) - else is nop - 1 clock - jmp *sr: - 0b10110100ssss0000 - 0x34s0 - JuMP : - pc <- sr - nop on pc - 2 clocks - itp rm: - 0b01110001mmmm0000 - 0x71m0 - InTerruPt : - Raises interrupt of id - rm - 6 clocks - dsi : - 0b0111001000000000 - 0x7200 - DiSable Interrupts: - Disables interrupts - 1 clock - eni : - 0b0111001100000000 - 0x7300 - ENable Interrupts: - Enables interrupts - 1 clock - rgi rm: - 0b01110000mmmm0000 - 0x70m0 - ReGister Interrupt : - rm should be as follows: - bit 0 : raisable by itp - bit 1 : raisable by bus - Sets rm to id on succes, - and 0xFF on failure - 2 clocks +instruction format: + big endian + 16bits + +registers: + r0-r12 (mov 0x0-0xc): + general purpose + 8 bits + r13-r15 (mov 0xd-0xf): + Interrupt reserved + 8 bits + ac,pr (special 0x0,1): + accumulator, progam counter + 16bits + ac0-1,pc0-1 (lds/sts 0x0-1,0x2-3): + accumulator, progam counter + 8-8bits (lower-upper) + id (special 0x2): + interrupt data, + set by the interrupt + if raised by bus + 8bits + in (Special 0x3): + interrupt register, + contains the type of + interrupt + 4bits - bits 0-3 will always be 0 + t bit: + is set by comp ops + 1bit +calling conventions: + r0-r1 : return registers + r2-r11: call args + r12 : stack pos + r13-15:interrupt reserved (only adressable in interrupt mode) + caller pushes desired return addr + to stack, callee jumps to it + +Interrupts: + Hardware interrupts: + 0x0 : Invalid instruction + The 15 other interrupts are free to + define by the user + On interrupt (either called through + the bus or itp) +startup: + the cpu will look + at adress 0x0,and + expects to find : + -0x0-1: adress of + the starting + point,will be + jumped to + -0x2-3: adress of + the stack, the + adress will be + read here + everytime + -0x4-5:adress of + the interrupt + handler, the + adress will be + read here + everytime + When an interrupt is raised, the cpu will allow acces + to r12-15 and push the resume adress to stack (in + order pc0 then pc1) + +instructions : + format: + rm,rn: general purpose registers + #imm:immediate signed 8bit value + *rm:memory at adress (pc+rm) + *#imm:memory at adress (pc+#imm) + sr: pr,ac + sr0-1: pr0-1/ac0-1, in/id + st: stack adress that is at 0x2, + abreviation for explanation only + nop : + 0b0000000000000000 + 0x0000 + No-OP: + Does nothing + 1 clock + mov rm,rn: + 0b00100000mmmmnnnn + 0x20mn + MOVe : + rm <- rn + 1 clock + mov rn,#imm: + 0b1000nnnnmmmmmmmm + 0x8nmm + rn <- #imm + 1 clock + mov rm,*rn: + 0b11000000mmmmnnnn + 0xB0mn + rm <- *(pc+rn) + 1 clock + mov rn,*#imm: + 0b1001nnnnmmmmmmmm + 0x9nmm + rn <- *(pc+#imm) + 1 clock + mov *rm,rn: + 0b11000001mmmmnnnn + 0xB1mn + *(pc+rm) <- rn + 1 clock + mov *#imm,rn: + 0b1010nnnnmmmmmmmm + 0xAnmm + *(pc+#imm) <- rn + 1 clock + mov *rm,*rn: + 0b11000010mmmmnnnn + 0xB2mn + *(pc+rm) <- *(pc+rn) + 1 clock + mmv rm, *sr: + 0b11000011mmmmssss + 0xB3ms + Memory MoVe + rm <- *sr + Meant to be used with the accumulator + 1 clock + mmv *sr, rm: + 0b11000100ssssmmmm + 0xB4sm + *sr <- rm + Meant to be used with the accumulator + 1 clock + psh rm: + 0b11000101mmmm0000 + 0xB5m0 + PuSH to stack: + *(st+r11) <- rm + r11 <- r11+1 + 2 clocks + pop rm: + 0b11000110mmmm0000 + 0xB6m0 + POP from stack + r11 <- r11-1 + rm <- *(st+r11) + 2 clocks + lds sr0-1,rm: + 0b11100000ssssmmmm + 0xE0sm + LoaD Special : + sr0-1 <- rm + nop on pc + 1 clock + sts rm,sr0-1: + 0b11100001mmmmssss + 0xE1ms + STore Special : + rm <- sr0-1 + 1 clock + add rn,rm: + 0b01000000nnnnmmmm + 0x40nm + ADD : + rn <- rn+rm + 1 clock + add r0,#imm: + 0b01001000mmmmmmmm + 0x48mm + r0 <- r0+#imm + 1 clock + sad sr0-1,rm: + 0b11100010ssssmmmm + 0xE2sm + Special ADd + sr0-1 <- sr0-1+rm + (16bit add) + nop on pc + 1 clock + sub rm,rn: + 0b01000001mmmmnnnn + 0x41mn + SUBstract : + rm <- rm-rn + 1 clock + shl rm: + 0b01000010mmmm0000 + 0x42m0 + SHift Left + rm <- rm<<1 + pure shift, no keep sign + 1 clock + shr rm: + 0b01000011mmmm0000 + 0x43m0 + SHift Right + rm <- rm>>1 + pure shift, no keep sign + 1 clock + and rm,rn: + 0b01000100mmmmnnnn + 0x44mn + binary AND : + rm <- rm&rn + 1 clock + or rm,rn: + 0b01000101mmmmnnnn + 0x45mn + binary OR : + rm <- rm|rn + 1 clock + xor rm,rn: + 0b01000110mmmmnnnn + 0x46mn + binary eXclusive OR: + rm <- rm^rn + 1 clock + not rm: + 0b01000111mmmmnnnn + 0x47mn + binary NOT : + rm <- !rm + binary not + 1 clock + rtb : + 0b0110000000000000 + 0x6000 + Reset T Bit : + t <- 0 + 1 clock + gth rm,rn: + 0b01100001mmmmnnnn + 0x61mn + Greater THan : + t <- rm > rn ? 1:0 + 1 clock + gts rm,rn: + 0b01100100mmmmnnn + 0x64mn + Greater Than (Signed): + t <- rm > rn ? 1:0 + (signed) (signed) + 1 clock + eql rm,rn: + 0b01100010mmmmnnnn + 0x62mn + EQuaL : + t <- rm == rn ? 1:0 + 1 clock + stb rm: + 0b01100011mmmm0000 + 0x63m0 + Store T Bit: + rm <- t + 1 clock + br *rm: + 0b10110010mmmm0000 + 0x32m0 + BRanch : + pc <- pc + rm *2 + (signed) + 1 clock + br *#imm: + 0b10110000mmmmmmmm + 0x30mm + pc <- pc + #imm*2 + 1 clock + bt *rm: + 0b10110101mmmm0000 + 0x35m0 + Branch if True: + If t == 1, + pc <- pc + rm *2 + (signed) + else is nop + 1 clock + bt *#imm: + 0b10110001mmmmmmmm + 0x31mm + If t == 1, + pc <- pc + #imm*2 + else is nop + 1 clock + bf *rm: + 0b10110011mmmm0000 + 0x33m0 + Branch if False: + If t == 0, + pc <- pc + rm *2 + (signed) + else is nop + 1 clock + jmp *sr: + 0b10110100ssss0000 + 0x34s0 + JuMP : + pc <- sr + nop on pc + 2 clocks + itp rm: + 0b01110001mmmm0000 + 0x71m0 + InTerruPt : + Raises interrupt of id + rm + 6 clocks + dsi : + 0b0111001000000000 + 0x7200 + DiSable Interrupts: + Disables interrupts + 1 clock + eni : + 0b0111001100000000 + 0x7300 + ENable Interrupts: + Enables interrupts + 1 clock + rgi rm: + 0b01110000mmmm0000 + 0x70m0 + ReGister Interrupt : + rm should be as follows: + bit 0 : raisable by itp + bit 1 : raisable by bus + Sets rm to id on succes, + and 0xFF on failure + 2 clocks