mirror of
https://git.planet-casio.com/Lephenixnoir/fxsdk.git
synced 2024-12-29 13:03:37 +01:00
25db504c22
Almost-complete implementation of fxos, the disassembler in particular is now able to detect syscalls and register addresses on the fly, plus support for SH4-only instructions.
220 lines
7.1 KiB
Text
220 lines
7.1 KiB
Text
# Instruction decoding table: 'sh3'
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# Format: [01nmdi]{16}, followed by the mnemonic and the list of arguments.
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# There should be at most one series of each argument letter in the opcode.
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#
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# Possible argument strings are predefined and include:
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# rn rm #imm
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# jump8 jump12 disp pcdisp
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# @rn @rm @rn+ @rm+ @-rn
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# @(disp,rn) @(disp,rm) @(r0,rn) @(r0,rm) @(disp,gbr)
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#
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# The disassembler substitutes some elements as follows:
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# rn -> value of the "n"-sequence
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# rm -> value of the "m"-sequence
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# #imm -> value of the "i"-sequence
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# disp -> value of the "d"-sequence
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# jump8 -> value of the 8-bit "d"-sequence plus value of PC
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# jump12 -> value of the 12-bit "d"-sequence plus value of PC
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# pcdisp -> same as "jump8", but also prints pointed value (for data)
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0000000001001000 clrs
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0000000000001000 clrt
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0000000000101000 clrmac
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0000000000011001 div0u
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0000000000111000 ldtlb
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0000000000001001 nop
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0000000000101011 rte
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0000000000001011 rts
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0000000001011000 sets
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0000000000011000 sett
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0000000000011011 sleep
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0100nnnn00010101 cmp/pl rn
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0100nnnn00010001 cmp/pz rn
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0100nnnn00010000 dt rn
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0000nnnn00101001 movt rn
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0100nnnn00000100 rotl rn
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0100nnnn00000101 rotr rn
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0100nnnn00100100 rotcl rn
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0100nnnn00100101 rotcr rn
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0100nnnn00100000 shal rn
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0100nnnn00100001 shar rn
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0100nnnn00000000 shll rn
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0100nnnn00000001 shlr rn
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0100nnnn00001000 shll2 rn
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0100nnnn00001001 shlr2 rn
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0100nnnn00011000 shll8 rn
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0100nnnn00011001 shlr8 rn
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0100nnnn00101000 shll16 rn
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0100nnnn00101001 shlr16 rn
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0011nnnnmmmm1100 add rm, rn
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0011nnnnmmmm1110 addc rm, rn
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0011nnnnmmmm1111 addv rm, rn
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0010nnnnmmmm1001 and rm, rn
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0011nnnnmmmm0000 cmp/eq rm, rn
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0011nnnnmmmm0010 cmp/hs rm, rn
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0011nnnnmmmm0011 cmp/ge rm, rn
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0011nnnnmmmm0110 cmp/hi rm, rn
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0011nnnnmmmm0111 cmp/gt rm, rn
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0010nnnnmmmm1100 cmp/str rm, rn
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0011nnnnmmmm0100 div1 rm, rn
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0010nnnnmmmm0111 div0s rm, rn
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0011nnnnmmmm1101 dmuls.l rm, rn
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0011nnnnmmmm0101 dmulu.l rm, rn
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0110nnnnmmmm1110 exts.b rm, rn
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0110nnnnmmmm1111 exts.w rm, rn
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0110nnnnmmmm1100 extu.b rm, rn
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0110nnnnmmmm1101 extu.w rm, rn
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0110nnnnmmmm0011 mov rm, rn
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0000nnnnmmmm0111 mul.l rm, rn
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0010nnnnmmmm1111 muls.w rm, rn
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0010nnnnmmmm1110 mulu.w rm, rn
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0110nnnnmmmm1011 neg rm, rn
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0110nnnnmmmm1010 negc rm, rn
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0110nnnnmmmm0111 not rm, rn
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0010nnnnmmmm1011 or rm, rn
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0100nnnnmmmm1100 shad rm, rn
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0100nnnnmmmm1101 shld rm, rn
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0011nnnnmmmm1000 sub rm, rn
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0011nnnnmmmm1010 subc rm, rn
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0011nnnnmmmm1011 subv rm, rn
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0110nnnnmmmm1000 swap.b rm, rn
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0110nnnnmmmm1001 swap.w rm, rn
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0010nnnnmmmm1000 tst rm, rn
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0010nnnnmmmm1010 xor rm, rn
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0010nnnnmmmm1101 xtrct rm, rn
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0100mmmm00001110 ldc rm, sr
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0100mmmm00011110 ldc rm, gbr
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0100mmmm00101110 ldc rm, vbr
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0100mmmm00111110 ldc rm, ssr
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0100mmmm01001110 ldc rm, spc
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0100mmmm10001110 ldc rm, r0_bank
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0100mmmm10011110 ldc rm, r1_bank
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0100mmmm10101110 ldc rm, r2_bank
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0100mmmm10111110 ldc rm, r3_bank
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0100mmmm11001110 ldc rm, r4_bank
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0100mmmm11011110 ldc rm, r5_bank
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0100mmmm11101110 ldc rm, r6_bank
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0100mmmm11111110 ldc rm, r7_bank
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0100mmmm00001010 lds rm, mach
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0100mmmm00011010 lds rm, macl
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0100mmmm00101010 lds rm, pr
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0000nnnn00000010 stc sr, rn
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0000nnnn00010010 stc gbr, rn
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0000nnnn00100010 stc vbr, rn
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0000nnnn00110010 stc ssr, rn
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0000nnnn01000010 stc spc, rn
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0000nnnn10000010 stc r0_bank, rn
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0000nnnn10010010 stc r1_bank, rn
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0000nnnn10100010 stc r2_bank, rn
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0000nnnn10110010 stc r3_bank, rn
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0000nnnn11000010 stc r4_bank, rn
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0000nnnn11010010 stc r5_bank, rn
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0000nnnn11100010 stc r6_bank, rn
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0000nnnn11110010 stc r7_bank, rn
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0000nnnn00001010 sts mach, rn
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0000nnnn00011010 sts macl, rn
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0000nnnn00101010 sts pr, rn
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0100nnnn00101011 jmp @rn
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0100nnnn00001011 jsr @rn
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0000nnnn10000011 pref @rn
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0100nnnn00011011 tas.b @rn
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0010nnnnmmmm0000 mov.b rm, @rn
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0010nnnnmmmm0001 mov.w rm, @rn
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0010nnnnmmmm0010 mov.l rm, @rn
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0110nnnnmmmm0000 mov.b @rm, rn
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0110nnnnmmmm0001 mov.w @rm, rn
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0110nnnnmmmm0010 mov.l @rm, rn
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0000nnnnmmmm1111 mac.l @rm+, @rn+
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0100nnnnmmmm1111 mac.w @rm+, @rn+
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0110nnnnmmmm0100 mov.b @rm+, rn
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0110nnnnmmmm0101 mov.w @rm+, rn
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0110nnnnmmmm0110 mov.l @rm+, rn
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0100mmmm00000111 ldc.l @rm+, sr
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0100mmmm00010111 ldc.l @rm+, gbr
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0100mmmm00100111 ldc.l @rm+, vbr
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0100mmmm00110111 ldc.l @rm+, ssr
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0100mmmm01000111 ldc.l @rm+, spc
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0100mmmm10000111 ldc.l @rm+, r0_bank
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0100mmmm10010111 ldc.l @rm+, r1_bank
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0100mmmm10100111 ldc.l @rm+, r2_bank
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0100mmmm10110111 ldc.l @rm+, r3_bank
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0100mmmm11000111 ldc.l @rm+, r4_bank
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0100mmmm11010111 ldc.l @rm+, r5_bank
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0100mmmm11100111 ldc.l @rm+, r6_bank
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0100mmmm11110111 ldc.l @rm+, r7_bank
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0100mmmm00000110 lds.l @rm+, mach
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0100mmmm00010110 lds.l @rm+, macl
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0100mmmm00100110 lds.l @rm+, pr
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0010nnnnmmmm0100 mov.b rm, @-rn
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0010nnnnmmmm0101 mov.w rm, @-rn
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0010nnnnmmmm0110 mov.l rm, @-rn
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0100nnnn00000011 stc.l sr, @-rn
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0100nnnn00010011 stc.l gbr, @-rn
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0100nnnn00100011 stc.l vbr, @-rn
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0100nnnn00110011 stc.l ssr, @-rn
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0100nnnn01000011 stc.l spc, @-rn
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0100nnnn10000011 stc.l r0_bank, @-rn
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0100nnnn10010011 stc.l r1_bank, @-rn
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0100nnnn10100011 stc.l r2_bank, @-rn
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0100nnnn10110011 stc.l r3_bank, @-rn
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0100nnnn11000011 stc.l r4_bank, @-rn
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0100nnnn11010011 stc.l r5_bank, @-rn
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0100nnnn11100011 stc.l r6_bank, @-rn
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0100nnnn11110011 stc.l r7_bank, @-rn
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0100nnnn00000010 sts.l mach, @-rn
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0100nnnn00010010 sts.l macl, @-rn
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0100nnnn00100010 sts.l pr, @-rn
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10000000nnnndddd mov.b r0, @(disp, rn)
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10000001nnnndddd mov.w r0, @(disp, rn)
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0001nnnnmmmmdddd mov.l rm, @(disp, rn)
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10000100mmmmdddd mov.b @(disp, rm), r0
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10000101mmmmdddd mov.w @(disp, rm), r0
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0101nnnnmmmmdddd mov.l @(disp, rm), rn
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0000nnnnmmmm0100 mov.b rm, @(r0, rn)
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0000nnnnmmmm0101 mov.w rm, @(r0, rn)
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0000nnnnmmmm0110 mov.l rm, @(r0, rn)
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0000nnnnmmmm1100 mov.b @(r0, rm), rn
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0000nnnnmmmm1101 mov.w @(r0, rm), rn
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0000nnnnmmmm1110 mov.l @(r0, rm), rn
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11000000dddddddd mov.b r0, @(disp, gbr)
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11000001dddddddd mov.w r0, @(disp, gbr)
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11000010dddddddd mov.l r0, @(disp, gbr)
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11000100dddddddd mov.b @(disp, gbr), r0
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11000101dddddddd mov.w @(disp, gbr), r0
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11000110dddddddd mov.l @(disp, gbr), r0
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11001101iiiiiiii and.b #imm, @(r0, gbr)
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11001111iiiiiiii or.b #imm, @(r0, gbr)
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11001100iiiiiiii tst.b #imm, @(r0, gbr)
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11001110iiiiiiii xor.b #imm, @(r0, gbr)
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1001nnnndddddddd mov.w pcdisp, rn
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1101nnnndddddddd mov.l pcdisp, rn
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11000111dddddddd mova pcdisp, r0
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0000mmmm00100011 braf rm
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0000mmmm00000011 bsrf rm
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10001011dddddddd bf jump8
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10001111dddddddd bf/s jump8
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10001001dddddddd bt jump8
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10001101dddddddd bt/s jump8
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1010dddddddddddd bra jump12
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1011dddddddddddd bsr jump12
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0111nnnniiiiiiii add #imm, rn
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11001001iiiiiiii and #imm, r0
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10001000iiiiiiii cmp/eq #imm, r0
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1110nnnniiiiiiii mov #imm, rn
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11001011iiiiiiii or #imm, r0
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11001000iiiiiiii tst #imm, r0
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11001010iiiiiiii xor #imm, r0
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11000011iiiiiiii trapa #imm
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