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support data loading in ILRAM, XRAM and YRAM
This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
This commit is contained in:
Lephe
parent
bb77e4588d
commit
15558c8fb3
4 changed files with 117 additions and 22 deletions
64
fx9860g.ld
64
fx9860g.ld
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@ -15,19 +15,24 @@ MEMORY
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{
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/* Userspace mapping of the add-in (0x200 B are for the G1A header).
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220k is the maximum amount of simultaneously-mappable code */
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rom (rx): o = 0x00300200, l = 220k
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rom (rx): o = 0x00300200, l = 220k
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/* This is mapped to RAM; 8k on SH3, apparently 32k on SH4 */
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ram (rw): o = 0x08100000, l = 8k
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ram (rw): o = 0x08100000, l = 8k
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/* gint's VBR space, mentioned here for completeness */
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vbr (rwx): o = 0x8800e000, l = 5k
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vbr (rwx): o = 0x8800e000, l = 5k
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/* Some RAM region from P1 area; gint's data will reside here */
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rram (rwx): o = 0x8800f400, l = 3k
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rram (rwx): o = 0x8800f400, l = 3k
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/* On-chip IL memory */
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ilram (rwx): o = 0xe5200000, l = 4k
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/* On-chip X and Y memory */
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xram (rwx): o = 0xe5007000, l = 8k
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yram (rwx): o = 0xe5017000, l = 8k
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}
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SECTIONS
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{
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/*
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** ROM sections
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** ROM sections
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*/
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/* First address to be mapped to ROM (including G1A header) */
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@ -94,13 +99,16 @@ SECTIONS
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- Resources or assets from fxconv or similar converters
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- Data marked read-only by the compiler (.rodata and .rodata.*) */
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.rodata : SUBALIGN(4) {
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/* Put these first, they need to be 4-aligned */
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*(.rodata.4)
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*(.rodata .rodata.*)
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} > rom
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/*
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** RAM sections
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** RAM sections
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*/
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. = ORIGIN(ram);
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@ -142,12 +150,48 @@ SECTIONS
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_sdata = SIZEOF(.data) + SIZEOF(.data.4);
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/* On-chip memory sections: IL, X and Y memory */
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. = ORIGIN(ilram);
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.ilram ALIGN(4) : ALIGN(4) {
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_lilram = LOADADDR(.ilram);
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_rilram = . ;
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*(.ilram)
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. = ALIGN(16);
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} > ilram AT> rom
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. = ORIGIN(xram);
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.xram ALIGN(4) : ALIGN(4) {
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_lxram = LOADADDR(.xram);
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_rxram = . ;
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*(.xram)
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. = ALIGN(16);
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} > xram AT> rom
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. = ORIGIN(yram);
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.yram ALIGN(4) : ALIGN(4) {
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_lyram = LOADADDR(.yram);
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_ryram = . ;
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*(.yram)
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. = ALIGN(16);
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} > yram AT> rom
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_silram = SIZEOF(.ilram);
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_sxram = SIZEOF(.xram);
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_syram = SIZEOF(.yram);
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/*
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** RRAM sections
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** 8800e000:4k VBR space
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** 8800f000:4k .gint.data and .gint.bss
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** RRAM sections
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** 8800e000:4k VBR space
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** 8800f000:4k .gint.data and .gint.bss
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*/
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/* VBR address: let's just start at the beginning of the RRAM area.
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@ -185,7 +229,7 @@ SECTIONS
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/*
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** Other sections
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** Other sections
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*/
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/* Unwanted sections going to meet Dave Null:
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63
fxcg50.ld
63
fxcg50.ld
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@ -13,20 +13,25 @@ ENTRY(_start)
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MEMORY
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{
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/* Userspace mapping of the add-in (without G3A header) */
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rom (rx): o = 0x00300000, l = 220k
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rom (rx): o = 0x00300000, l = 220k
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/* Static RAM; stack grows down from the end of this region.
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The first 0x2000 bytes are reserved by gint, see below */
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ram (rw): o = 0x08102000, l = 512k
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ram (rw): o = 0x08102000, l = 512k
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/* gint's VBR space, mentioned here for completeness */
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vbr (rwx): o = 0x8c160000, l = 5k
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vbr (rwx): o = 0x8c160000, l = 5k
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/* Some RAM region from P1 area; gint's data will reside here */
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rram (rwx): o = 0x8c161400, l = 3k
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rram (rwx): o = 0x8c161400, l = 3k
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/* On-chip IL memory */
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ilram (rwx): o = 0xe5200000, l = 4k
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/* On-chip X and Y memory */
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xram (rwx): o = 0xe5007000, l = 8k
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yram (rwx): o = 0xe5017000, l = 8k
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}
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SECTIONS
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{
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/*
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** ROM sections
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** ROM sections
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*/
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/* First address to be mapped to ROM */
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@ -87,7 +92,7 @@ SECTIONS
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- Data marked read-only by the compiler (.rodata and .rodata.*) */
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.rodata : SUBALIGN(4) {
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/* Put these first, they need to be 4-aligned */
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*(.rodata.assets)
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*(.rodata.4)
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*(.rodata .rodata.*)
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} > rom
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@ -95,7 +100,7 @@ SECTIONS
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/*
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** RAM sections
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** RAM sections
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*/
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. = ORIGIN(ram);
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@ -130,12 +135,48 @@ SECTIONS
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_sdata = SIZEOF(.data) + SIZEOF(.data.4);
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/* On-chip memory sections: IL, X and Y memory */
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. = ORIGIN(ilram);
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.ilram ALIGN(4) : ALIGN(4) {
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_lilram = LOADADDR(.ilram);
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_rilram = . ;
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*(.ilram)
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. = ALIGN(16);
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} > ilram AT> rom
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. = ORIGIN(xram);
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.xram ALIGN(4) : ALIGN(4) {
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_lxram = LOADADDR(.xram);
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_rxram = . ;
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*(.xram)
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. = ALIGN(16);
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} > xram AT> rom
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. = ORIGIN(yram);
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.yram ALIGN(4) : ALIGN(4) {
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_lyram = LOADADDR(.yram);
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_ryram = . ;
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*(.yram)
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. = ALIGN(16);
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} > yram AT> rom
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_silram = SIZEOF(.ilram);
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_sxram = SIZEOF(.xram);
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_syram = SIZEOF(.yram);
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/*
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** gint-related sections
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** 8c160000:4k VBR space
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** 8c161000:4k .gint.data and .gint.bss
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** gint-related sections
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** 8c160000:4k VBR space
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** 8c161000:4k .gint.data and .gint.bss
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*/
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/* VBR address: let's just start at the beginning of the RAM area.
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@ -173,7 +214,7 @@ SECTIONS
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/*
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** Other sections
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** Other sections
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*/
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/* Unwanted sections going to meet Dave Null:
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@ -13,6 +13,10 @@
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/* Additional sections that are only needed on SH3 */
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#define GDATA3 __attribute__((section(".gint.data.sh3")))
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#define GBSS3 __attribute__((section(".gint.bss.sh3")))
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/* Objects for the ILRAM, XRAM and YRAM regions */
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#define GILRAM __attribute__((section(".ilram")))
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#define GXRAM __attribute__((section(".xram")))
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#define GYRAM __attribute__((section(".yram")))
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/* Unused parameters or variables */
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#define GUNUSED __attribute__((unused))
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@ -20,6 +20,9 @@ extern uint32_t
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brom, srom, /* Limits of ROM mappings */
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lgdata, sgdata, rgdata, /* gint's data section */
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ldata, sdata, rdata, /* User's data section */
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lilram, silram, rilram, /* IL memory section */
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lxram, sxram, rxram, /* X memory section */
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lyram, syram, ryram, /* Y memory section */
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sbss, rbss, /* User's BSS section */
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btors, mtors, etors; /* Constructor/destructor arrays */
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extern gint_driver_t
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@ -120,7 +123,10 @@ int start(int isappli, int optnum)
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/* Load data sections and wipe the bss section. This has to be done
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first for static and global variables to be initialized */
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regcpy(lgdata, sgdata, rgdata);
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regcpy(ldata, sdata, rdata);
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regcpy(ldata, sdata, rdata);
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regcpy(lilram, silram, rilram);
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regcpy(lxram, sxram, rxram);
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regcpy(lyram, syram, ryram);
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regclr(rbss, sbss);
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bootlog_loaded();
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