mirror of
https://git.planet-casio.com/Lephenixnoir/gint.git
synced 2024-12-29 13:03:36 +01:00
support data loading in ILRAM, XRAM and YRAM
This change adds support for three sections .ilram, .xram and .yram, along with three macros GILRAM, GXRAM and GYRAM, that can be used to statically load data to on-chip memory.
This commit is contained in:
parent
bb77e4588d
commit
15558c8fb3
4 changed files with 117 additions and 22 deletions
44
fx9860g.ld
44
fx9860g.ld
|
@ -22,6 +22,11 @@ MEMORY
|
||||||
vbr (rwx): o = 0x8800e000, l = 5k
|
vbr (rwx): o = 0x8800e000, l = 5k
|
||||||
/* Some RAM region from P1 area; gint's data will reside here */
|
/* Some RAM region from P1 area; gint's data will reside here */
|
||||||
rram (rwx): o = 0x8800f400, l = 3k
|
rram (rwx): o = 0x8800f400, l = 3k
|
||||||
|
/* On-chip IL memory */
|
||||||
|
ilram (rwx): o = 0xe5200000, l = 4k
|
||||||
|
/* On-chip X and Y memory */
|
||||||
|
xram (rwx): o = 0xe5007000, l = 8k
|
||||||
|
yram (rwx): o = 0xe5017000, l = 8k
|
||||||
}
|
}
|
||||||
|
|
||||||
SECTIONS
|
SECTIONS
|
||||||
|
@ -94,6 +99,9 @@ SECTIONS
|
||||||
- Resources or assets from fxconv or similar converters
|
- Resources or assets from fxconv or similar converters
|
||||||
- Data marked read-only by the compiler (.rodata and .rodata.*) */
|
- Data marked read-only by the compiler (.rodata and .rodata.*) */
|
||||||
.rodata : SUBALIGN(4) {
|
.rodata : SUBALIGN(4) {
|
||||||
|
/* Put these first, they need to be 4-aligned */
|
||||||
|
*(.rodata.4)
|
||||||
|
|
||||||
*(.rodata .rodata.*)
|
*(.rodata .rodata.*)
|
||||||
} > rom
|
} > rom
|
||||||
|
|
||||||
|
@ -142,6 +150,42 @@ SECTIONS
|
||||||
|
|
||||||
_sdata = SIZEOF(.data) + SIZEOF(.data.4);
|
_sdata = SIZEOF(.data) + SIZEOF(.data.4);
|
||||||
|
|
||||||
|
/* On-chip memory sections: IL, X and Y memory */
|
||||||
|
|
||||||
|
. = ORIGIN(ilram);
|
||||||
|
.ilram ALIGN(4) : ALIGN(4) {
|
||||||
|
_lilram = LOADADDR(.ilram);
|
||||||
|
_rilram = . ;
|
||||||
|
|
||||||
|
*(.ilram)
|
||||||
|
|
||||||
|
. = ALIGN(16);
|
||||||
|
} > ilram AT> rom
|
||||||
|
|
||||||
|
. = ORIGIN(xram);
|
||||||
|
.xram ALIGN(4) : ALIGN(4) {
|
||||||
|
_lxram = LOADADDR(.xram);
|
||||||
|
_rxram = . ;
|
||||||
|
|
||||||
|
*(.xram)
|
||||||
|
|
||||||
|
. = ALIGN(16);
|
||||||
|
} > xram AT> rom
|
||||||
|
|
||||||
|
. = ORIGIN(yram);
|
||||||
|
.yram ALIGN(4) : ALIGN(4) {
|
||||||
|
_lyram = LOADADDR(.yram);
|
||||||
|
_ryram = . ;
|
||||||
|
|
||||||
|
*(.yram)
|
||||||
|
|
||||||
|
. = ALIGN(16);
|
||||||
|
} > yram AT> rom
|
||||||
|
|
||||||
|
_silram = SIZEOF(.ilram);
|
||||||
|
_sxram = SIZEOF(.xram);
|
||||||
|
_syram = SIZEOF(.yram);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
43
fxcg50.ld
43
fxcg50.ld
|
@ -21,6 +21,11 @@ MEMORY
|
||||||
vbr (rwx): o = 0x8c160000, l = 5k
|
vbr (rwx): o = 0x8c160000, l = 5k
|
||||||
/* Some RAM region from P1 area; gint's data will reside here */
|
/* Some RAM region from P1 area; gint's data will reside here */
|
||||||
rram (rwx): o = 0x8c161400, l = 3k
|
rram (rwx): o = 0x8c161400, l = 3k
|
||||||
|
/* On-chip IL memory */
|
||||||
|
ilram (rwx): o = 0xe5200000, l = 4k
|
||||||
|
/* On-chip X and Y memory */
|
||||||
|
xram (rwx): o = 0xe5007000, l = 8k
|
||||||
|
yram (rwx): o = 0xe5017000, l = 8k
|
||||||
}
|
}
|
||||||
|
|
||||||
SECTIONS
|
SECTIONS
|
||||||
|
@ -87,7 +92,7 @@ SECTIONS
|
||||||
- Data marked read-only by the compiler (.rodata and .rodata.*) */
|
- Data marked read-only by the compiler (.rodata and .rodata.*) */
|
||||||
.rodata : SUBALIGN(4) {
|
.rodata : SUBALIGN(4) {
|
||||||
/* Put these first, they need to be 4-aligned */
|
/* Put these first, they need to be 4-aligned */
|
||||||
*(.rodata.assets)
|
*(.rodata.4)
|
||||||
|
|
||||||
*(.rodata .rodata.*)
|
*(.rodata .rodata.*)
|
||||||
} > rom
|
} > rom
|
||||||
|
@ -130,6 +135,42 @@ SECTIONS
|
||||||
|
|
||||||
_sdata = SIZEOF(.data) + SIZEOF(.data.4);
|
_sdata = SIZEOF(.data) + SIZEOF(.data.4);
|
||||||
|
|
||||||
|
/* On-chip memory sections: IL, X and Y memory */
|
||||||
|
|
||||||
|
. = ORIGIN(ilram);
|
||||||
|
.ilram ALIGN(4) : ALIGN(4) {
|
||||||
|
_lilram = LOADADDR(.ilram);
|
||||||
|
_rilram = . ;
|
||||||
|
|
||||||
|
*(.ilram)
|
||||||
|
|
||||||
|
. = ALIGN(16);
|
||||||
|
} > ilram AT> rom
|
||||||
|
|
||||||
|
. = ORIGIN(xram);
|
||||||
|
.xram ALIGN(4) : ALIGN(4) {
|
||||||
|
_lxram = LOADADDR(.xram);
|
||||||
|
_rxram = . ;
|
||||||
|
|
||||||
|
*(.xram)
|
||||||
|
|
||||||
|
. = ALIGN(16);
|
||||||
|
} > xram AT> rom
|
||||||
|
|
||||||
|
. = ORIGIN(yram);
|
||||||
|
.yram ALIGN(4) : ALIGN(4) {
|
||||||
|
_lyram = LOADADDR(.yram);
|
||||||
|
_ryram = . ;
|
||||||
|
|
||||||
|
*(.yram)
|
||||||
|
|
||||||
|
. = ALIGN(16);
|
||||||
|
} > yram AT> rom
|
||||||
|
|
||||||
|
_silram = SIZEOF(.ilram);
|
||||||
|
_sxram = SIZEOF(.xram);
|
||||||
|
_syram = SIZEOF(.yram);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -13,6 +13,10 @@
|
||||||
/* Additional sections that are only needed on SH3 */
|
/* Additional sections that are only needed on SH3 */
|
||||||
#define GDATA3 __attribute__((section(".gint.data.sh3")))
|
#define GDATA3 __attribute__((section(".gint.data.sh3")))
|
||||||
#define GBSS3 __attribute__((section(".gint.bss.sh3")))
|
#define GBSS3 __attribute__((section(".gint.bss.sh3")))
|
||||||
|
/* Objects for the ILRAM, XRAM and YRAM regions */
|
||||||
|
#define GILRAM __attribute__((section(".ilram")))
|
||||||
|
#define GXRAM __attribute__((section(".xram")))
|
||||||
|
#define GYRAM __attribute__((section(".yram")))
|
||||||
|
|
||||||
/* Unused parameters or variables */
|
/* Unused parameters or variables */
|
||||||
#define GUNUSED __attribute__((unused))
|
#define GUNUSED __attribute__((unused))
|
||||||
|
|
|
@ -20,6 +20,9 @@ extern uint32_t
|
||||||
brom, srom, /* Limits of ROM mappings */
|
brom, srom, /* Limits of ROM mappings */
|
||||||
lgdata, sgdata, rgdata, /* gint's data section */
|
lgdata, sgdata, rgdata, /* gint's data section */
|
||||||
ldata, sdata, rdata, /* User's data section */
|
ldata, sdata, rdata, /* User's data section */
|
||||||
|
lilram, silram, rilram, /* IL memory section */
|
||||||
|
lxram, sxram, rxram, /* X memory section */
|
||||||
|
lyram, syram, ryram, /* Y memory section */
|
||||||
sbss, rbss, /* User's BSS section */
|
sbss, rbss, /* User's BSS section */
|
||||||
btors, mtors, etors; /* Constructor/destructor arrays */
|
btors, mtors, etors; /* Constructor/destructor arrays */
|
||||||
extern gint_driver_t
|
extern gint_driver_t
|
||||||
|
@ -121,6 +124,9 @@ int start(int isappli, int optnum)
|
||||||
first for static and global variables to be initialized */
|
first for static and global variables to be initialized */
|
||||||
regcpy(lgdata, sgdata, rgdata);
|
regcpy(lgdata, sgdata, rgdata);
|
||||||
regcpy(ldata, sdata, rdata);
|
regcpy(ldata, sdata, rdata);
|
||||||
|
regcpy(lilram, silram, rilram);
|
||||||
|
regcpy(lxram, sxram, rxram);
|
||||||
|
regcpy(lyram, syram, ryram);
|
||||||
regclr(rbss, sbss);
|
regclr(rbss, sbss);
|
||||||
bootlog_loaded();
|
bootlog_loaded();
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue