From 302aeb5cdf9d4f3bc9d8ce030c99d2f298029765 Mon Sep 17 00:00:00 2001 From: Lephenixnoir Date: Tue, 11 Mar 2025 15:32:37 +0100 Subject: [PATCH] cpg: fix incorrect access size to SDMR3_CL2 and SDMR3_CL3 --- src/cpg/overclock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpg/overclock.c b/src/cpg/overclock.c index bf9b416..ac65ff2 100644 --- a/src/cpg/overclock.c +++ b/src/cpg/overclock.c @@ -21,8 +21,8 @@ // Low-level clock speed access //--- -#define SH7305_SDMR3_CL2 ((volatile uint8_t *)0xFEC15040) -#define SH7305_SDMR3_CL3 ((volatile uint8_t *)0xFEC15060) +#define SH7305_SDMR3_CL2 ((volatile uint16_t *)0xFEC15040) +#define SH7305_SDMR3_CL3 ((volatile uint16_t *)0xFEC15060) //--- // Predefined clock speeds