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scif: add the SH7705 and SH7305 SCIF descriptions
Co-authored-by: Slyvtt <pillot.sylvain@gmail.com>
This commit is contained in:
Lephe
parent
211d236496
commit
3bc3892524
2 changed files with 219 additions and 2 deletions
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@ -78,8 +78,7 @@ typedef volatile struct
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//---
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// SH7305 Pin Function Controller.
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// This is somewhat reminiscent of the SH7724, but there are many differences.
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// The official emulator is the basis for this module, with extra registers
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// added based on known differences with actual hardware (eg. few last ports).
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// The official emulator is the basis for this module.
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//---
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/* All port control registers (PCRx) have 2-bit entries specifying 4 pin modes:
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218
include/gint/mpu/scif.h
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218
include/gint/mpu/scif.h
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@ -0,0 +1,218 @@
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//---
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// gint:mpu:scif - Serial Communication Interface with FIFO (SCIF)
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//---
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#ifndef GINT_MPU_SCIF
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#define GINT_MPU_SCIF
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 SCIF (from: SH7705 manual, section 16)
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//---
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typedef volatile struct
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{
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/* Serial Mode Register */
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word_union(SCSMR,
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uint16_t :5;
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uint16_t SRC :3; /* Sampling Control */
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uint16_t CA :1; /* Communication Mode */
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uint16_t CHR :1; /* Character Length */
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uint16_t PE :1; /* Parity Enable */
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uint16_t OE :1; /* Parity Mode */
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uint16_t STOP :1; /* Stop Bit Length */
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uint16_t :1;
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uint16_t CKS :2; /* Clock Select */
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);
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pad(0x2);
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/* Bit Rate Register */
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uint8_t SCBRR;
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pad(0x3);
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/* Serial Control Register */
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word_union(SCSCR,
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uint16_t :4;
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uint16_t TSIE :1; /* Transmit Data Stop Interrupt Enable */
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uint16_t ERIE :1; /* Receive Error Interrupt Enable */
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uint16_t BRIE :1; /* Break Interrupt Enable */
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uint16_t DRIE :1; /* Receive Data Ready Interrupt Enable */
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uint16_t TIE :1; /* Transmit Interrupt Enable */
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uint16_t RIE :1; /* Receive Interrupt Enable */
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uint16_t TE :1; /* Transmit Enable */
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uint16_t RE :1; /* Receive Mode */
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uint16_t :2;
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uint16_t CKE :2; /* Clock Enable */
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);
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pad(0x2);
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/* Transmit Data Stop Register */
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uint8_t SCTDSR;
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pad(0x3);
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/* FIFO Error Count Register */
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word_union(SCFER,
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uint16_t :2;
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uint16_t PER :6; /* Parity Error Count */
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uint16_t :2;
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uint16_t FER :6; /* Framing Error Count */
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);
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pad(0x2);
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/* Serial Status Register */
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word_union(SCSSR,
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uint16_t :6;
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uint16_t ORER :1; /* Overrun Error */
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uint16_t TSF :1; /* Transmit Data Stop */
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uint16_t ER :1; /* Receive Error */
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uint16_t TEND :1; /* Transmit End */
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uint16_t TDFE :1; /* Transmit FIFO Data Empty */
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uint16_t BRK :1; /* Break Detect */
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uint16_t FER :1; /* Framing Error */
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uint16_t PER :1; /* Parity Error */
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uint16_t RDF :1; /* Receive FIFO Data Full */
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uint16_t DR :1; /* Receive Data Ready */
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);
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pad(0x2);
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/* FIFO Control Register */
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word_union(SCFCR,
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uint16_t TSE :1; /* Transmit Data Stop Enable */
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uint16_t TCRST :1; /* Transmit Count Reset */
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uint16_t :3;
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uint16_t RSTRG :3; /* RTS Output Active Trigger */
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uint16_t RTRG :2; /* Receive FIFO Data Number Trigger */
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uint16_t TTRG :2; /* Transmit FIFO Data Number Trigger */
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uint16_t MCE :1; /* Modem Control Enable */
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uint16_t TFRST :1; /* Transmit FIFO Data Register Reset */
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uint16_t RFRST :1; /* Receive FIFO Data Register Reset */
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uint16_t LOOP :1; /* Loopback Test */
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);
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pad(0x2);
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/* FIFO Data Count Register */
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word_union(SCFDR,
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uint16_t :1;
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uint16_t T :7; /* Pending bytes in transmit FIFO */
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uint16_t :1;
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uint16_t R :7; /* Received bytes in receive FIFO */
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);
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pad(0x2);
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/* Serial FIFO Transmit Data Register (64 bytes rolling register) */
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uint8_t SCFTDR;
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pad(0x3);
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/* Serial FIFO Receive Data Register (64 bytes rolling register) */
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uint8_t SCFRDR;
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} GPACKED(4) sh7705_scif_t;
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#define SH7705_SCIF (*((sh7705_scif_t *)0xa4410000))
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//---
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// SH7305 SCIF (from: SH7305 emulator and SH7730 SCIF)
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// The module is very close to the SH7724 but it has a couple extra bits in
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// SCFCR, which shows that it is closer to the SH7730 SCIF.
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//---
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typedef volatile struct
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{
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/* Serial Mode Register */
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word_union(SCSMR,
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uint16_t :8;
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uint16_t CA :1; /* Communication Mode */
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uint16_t CHR :1; /* Character Length */
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uint16_t PE :1; /* Parity Enable */
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uint16_t OE :1; /* Parity Mode */
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uint16_t STOP :1; /* Stop Bit Length */
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uint16_t :1;
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uint16_t CKS :2; /* Clock Select */
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);
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pad(0x2);
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/* Serial Bit Rate Register */
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uint8_t SCBRR;
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pad(0x3);
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/* Serial Control Register */
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word_union(SCSCR,
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uint16_t :8;
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uint16_t TIE :1; /* Transmit Interrupt Enable */
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uint16_t RIE :1; /* Receive Interrupt Enable */
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uint16_t TE :1; /* Transmit Enable */
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uint16_t RE :1; /* Receive Mode */
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uint16_t REIE :1; /* Receive Error Interrupt Enable */
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uint16_t :1;
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uint16_t CKE :2; /* Clock Enable */
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);
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pad(0x2);
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/* Serial FIFO Transmit Data Register */
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uint8_t SCFTDR;
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pad(0x3);
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/* Serial FIFO Status Register */
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word_union(SCFSR,
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uint16_t const PERC :4; /* Number of Parity Errors */
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uint16_t const FERC :4; /* Number of Framing Errors */
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uint16_t ER :1; /* Receive Error */
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uint16_t TEND :1; /* Transmit End */
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uint16_t TDFE :1; /* Transmit FIFO Data Empty */
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uint16_t BRK :1; /* Break Detection */
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uint16_t const FER :1; /* Framing Error */
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uint16_t const PER :1; /* Parity Error */
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uint16_t RDF :1; /* Receive FIFO Data Full */
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uint16_t DR :1; /* Data Ready */
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);
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pad(0x2);
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/* Serial FIFO Receive Data Register */
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uint8_t SCFRDR;
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pad(0x3);
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/* Serial FIFO Control Register */
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word_union(SCFCR,
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uint16_t :5;
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uint16_t RSTRG :3; /* RTS Output Active Trigger */
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uint16_t RTRG :2; /* Receive FIFO Data Trigger */
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uint16_t TTRG :2; /* Transmit FIFO Data Trigger */
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uint16_t MCE :1; /* Model Control Enable */
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uint16_t TFRST :1; /* Transmit FIFO Data Register Reset */
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uint16_t RFRST :1; /* Receive FIFO Data Register Reset */
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uint16_t LOOP :1; /* Loopback Test */
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);
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pad(0x2);
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/* Serial FIFO Data Count Register */
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word_union(SCFDR,
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uint16_t :3;
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uint16_t TFDC :5; /* Number of Data Bytes in Transmit FIFO */
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uint16_t :3;
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uint16_t RFDC :5; /* Number of Data Bytes in Receive FIFO */
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);
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pad(0x6);
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/* Serial Line Status */
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word_union(SCLSR,
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uint16_t :15;
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uint16_t ORER :1; /* Overrun Error */
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);
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pad(0x2);
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} GPACKED(4) sh7305_scif_t;
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#define SH7305_SCIF (*((sh7305_scif_t *)0x04410000))
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_SCIF */
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