core: accept large add-ins and setup TLB management (UNSTABLE)

This change modifies the fx-CG 50 linker script to allow add-ins up to
2M and no longer complains about add-ins that don't fit in the TLB.

It also exposes the __TLB_LoadPTEH() syscall (%003 on fx9860g, %00c on
fxcg50) that answers TLB misses. This syscall can be called manually
from an add-in to load some pages and seems to work without problem.

However, this version does not provide any automatic TLB management,
some key areas of the kernel are still under TLB and some user code
(such as timer callbacks) is not! This version is suitable only for
add-ins smaller than 220k!

TODO

@@ -41,3 +41,4 @@ Future directions.
 * Serial communication
 * USB communication, using Yatis' reverse-engineering of the module
 * Make fx9860g projects work out of the box on fxcg50
+* Use the DSP to enhance parallel computation

fxcg50.ld

@@ -13,7 +13,7 @@ ENTRY(_start)
 MEMORY
 {
 	/* Userspace mapping of the add-in (without G3A header) */
-	rom   (rx):   o = 0x00300000, l = 220k
+	rom   (rx):   o = 0x00300000, l = 2M
 	/* Static RAM; stack grows down from the end of this region.
 	   The first 0x2000 bytes are reserved by gint, see below */
 	ram   (rw):   o = 0x08102000, l = 504k

include/gint/mmu.h

@@ -1,59 +1,27 @@
 //---
-//	core:mmu - MMU-related definitions
+//	gint:mmu - Memory Management Unit
-//
-//	gint does not touch the MMU because the risk of permanently wreaking
-//	the system is deemed too high. However, to ensure that the add-in runs
-//	properly, checks using read-only accesses to the MMU are performed.
 //---
 
-#ifndef GINT_CORE_MMU
+#ifndef GINT_MMU
-#define GINT_CORE_MMU
+#define GINT_MMU
 
-#include <gint/defs/attributes.h>
+#include <gint/mpu/mmu.h>
-#include <gint/defs/types.h>
 
 //---
 //	SH7705 TLB
 //---
 
-/* tlb_addr_t - address part of a TLB entry */
-typedef struct
-{
-	uint VPN	:22;
-	uint		:1;
-	uint V		:1;
-	uint ASID	:8;
-
-} GPACKED(4) tlb_addr_t;
-
-/* tlb_data_t - data part of a TLB entry */
-typedef struct
-{
-	uint		:3;
-	uint PPN	:19;
-	uint		:1;
-	uint V		:1;
-	uint		:1;
-	uint PR		:2;
-	uint SZ		:1;
-	uint C		:1;
-	uint D		:1;
-	uint SH		:1;
-	uint		:1;
-
-} GPACKED(4) tlb_data_t;
-
 /* tlb_addr() - get the P4 address of a TLB address entry
    @way  TLB way (0..3)
    @E    Entry number (0..31)
    Returns a pointer to the entry. */
-const tlb_addr_t *tlb_addr(uint way, uint E);
+tlb_addr_t const *tlb_addr(uint way, uint E);
 
 /* tlb_data() - get the P4 address of a TLB data entry
    @way  TLB way (0..3)
    @E    Entry number (0..31)
    Returns a pointer to the entry. */
-const tlb_data_t *tlb_data(uint way, uint E);
+tlb_data_t const *tlb_data(uint way, uint E);
 
 /* tlb_mapped_memory() - count amount of mapped memory
    This function returns the amount of mapped text and data segment memory, in
@@ -70,42 +38,15 @@ void tlb_mapped_memory(uint32_t *p_rom, uint32_t *p_ram);
 //	SH7305 Unified TLB
 //---
 
-/* utlb_addr_t - address part of a UTLB entry */
-typedef struct
-{
-	uint VPN	:22;
-	uint D		:1;
-	uint V		:1;
-	uint ASID	:8;
-
-} GPACKED(4) utlb_addr_t;
-
 /* utlb_addr() - get the P4 address of a UTLB address entry
    @E  Entry number (should be in range 0..63)
    Returns a pointer to the entry. */
 const utlb_addr_t *utlb_addr(uint E);
 
-/* utlb_data_t - data part of a UTLB entry */
-typedef struct
-{
-	uint		:3;
-	uint PPN	:19;
-	uint		:1;
-	uint V		:1;
-	uint SZ1	:1;
-	uint PR		:2;
-	uint SZ2	:1;
-	uint C		:1;
-	uint D		:1;
-	uint SH		:1;
-	uint WT		:1;
-
-} GPACKED(4) utlb_data_t;
-
 /* utlb_data() - get the P4 address of a UTLB data entry
    @E  Entry number (should be in range 0..63)
    Returns a pointer to the entry. */
-const utlb_data_t *utlb_data(uint E);
+utlb_data_t const *utlb_data(uint E);
 
 /* utlb_mapped_memory() - count amount of mapped memory
    This function returns the amount of mapped text and data segment memory, in
@@ -118,4 +59,4 @@ const utlb_data_t *utlb_data(uint E);
    @ram  Pointer to amount of mapped RAM */
 void utlb_mapped_memory(uint32_t *rom, uint32_t *ram);
 
-#endif /* GINT_CORE_MMU */
+#endif /* GINT_MMU */

include/gint/mpu/mmu.h

@@ -0,0 +1,80 @@
+//---
+//	gint:mpu:mmu - Memory Management Unit
+//
+//	The MMU mainly exposes the contents of the TLB for us to inspect.
+//	Functions to manipulate these are exposed by <gint/mmu.h>.
+//---
+
+#ifndef GINT_MPU_MMU
+#define GINT_MPU_MMU
+
+#include <gint/defs/attributes.h>
+#include <gint/defs/types.h>
+
+//---
+//	SH7705 TLB. Refer to:
+//	  "Renesas SH7705 Group Hardware Manual"
+//	  Section 3: "Memory Manaegement Unit (MMU)"
+//---
+
+/* tlb_addr_t - address part of a TLB entry */
+typedef struct
+{
+	uint VPN	:22;
+	uint		:1;
+	uint V		:1;
+	uint ASID	:8;
+
+} GPACKED(4) tlb_addr_t;
+
+/* tlb_data_t - data part of a TLB entry */
+typedef struct
+{
+	uint		:3;
+	uint PPN	:19;
+	uint		:1;
+	uint V		:1;
+	uint		:1;
+	uint PR		:2;
+	uint SZ		:1;
+	uint C		:1;
+	uint D		:1;
+	uint SH		:1;
+	uint		:1;
+
+} GPACKED(4) tlb_data_t;
+
+//---
+//	SH7305 TLB. Refer to:
+//	  "Renesas SH7724 User's Manual: Hardware"
+//	  Section 7: "Memory Management Unit (MMU)"
+//---
+
+/* utlb_addr_t - address part of a UTLB entry */
+typedef struct
+{
+	uint VPN	:22;
+	uint D		:1;
+	uint V		:1;
+	uint ASID	:8;
+
+} GPACKED(4) utlb_addr_t;
+
+/* utlb_data_t - data part of a UTLB entry */
+typedef struct
+{
+	uint		:3;
+	uint PPN	:19;
+	uint		:1;
+	uint V		:1;
+	uint SZ1	:1;
+	uint PR		:2;
+	uint SZ2	:1;
+	uint C		:1;
+	uint D		:1;
+	uint SH		:1;
+	uint WT		:1;
+
+} GPACKED(4) utlb_data_t;
+
+#endif /* GINT_MPU_MMU */

src/core/bootlog.c

@@ -5,7 +5,7 @@
 #include <gint/defs/types.h>
 #include <gint/std/string.h>
 #include <gint/std/stdio.h>
-#include <core/mmu.h>
+#include <gint/mmu.h>
 
 #include <gint/hardware.h>
 #include <gint/mpu/intc.h>

src/core/mmu.c

@@ -2,7 +2,7 @@
 //	gint:core:mmu - MMU-related definitions
 //---
 
-#include <core/mmu.h>
+#include <gint/mmu.h>
 #include <gint/hardware.h>
 
 //---

src/core/setup.c

@@ -14,7 +14,7 @@
 /* VBR address, from the linker script */
 extern char gint_vbr[];
 /* System's VBR address */
-GBSS static uint32_t system_vbr;
+GBSS uint32_t system_vbr;
 /* Size of exception and TLB handler */
 extern char gint_exch_tlbh_size;
 /* Driver table */

src/core/start.c

@@ -5,7 +5,7 @@
 #include <gint/defs/attributes.h>
 #include <gint/defs/types.h>
 #include <core/bootlog.h>
-#include <core/mmu.h>
+#include <gint/mmu.h>
 #include <gint/drivers.h>
 #include <gint/gint.h>
 #include <gint/hardware.h>
@@ -140,7 +140,7 @@ int start(int isappli, int optnum)
 	bootlog_mapped(rom, ram);
 
 	/* Cancel add-in execution if not all pages are mapped */
-	if(rom < (uint32_t)&srom) gint_panic(0x1040);
+//	if(rom < (uint32_t)&srom) gint_panic(0x1040);
 
 	/* Install gint and switch VBR */
 	gint_install();

src/core/syscalls.S

@@ -9,6 +9,9 @@
 **	* File system, because it's a mess and we might ruin the ROM.
 */
 
+/* TLB management */
+.global ___TLB_LoadPTEH
+
 /* Dynamic allocation */
 .global _malloc
 .global _free
@@ -50,6 +53,11 @@
 
 #ifdef FX9860G
 
+/* TLB Management */
+
+___TLB_LoadPTEH:
+	syscall(0x0003)
+
 /* Dynamic allocation */
 
 _malloc:
@@ -110,6 +118,11 @@ syscall_table:
 
 #ifdef FXCG50
 
+/* TLB Management */
+
+___TLB_LoadPTEH:
+	syscall(0x000c)
+
 /* Dynamic allocation */
 
 _malloc: