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https://git.planet-casio.com/Lephenixnoir/gint.git
synced 2024-12-29 13:03:36 +01:00
gdb: break before panicking in user code
This commit is contained in:
parent
6efcfa6018
commit
7d3663483f
1 changed files with 25 additions and 19 deletions
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@ -474,13 +474,13 @@ static struct {
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void* channel0_addr;
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void* channel0_addr;
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void* channel1_addr;
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void* channel1_addr;
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} gdb_single_step_backup = { false };
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} gdb_single_step_backup = { false };
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static void gdb_handle_single_step(gdb_cpu_state_t* cpu_state)
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static void gdb_handle_single_step(uint32_t pc, ubc_break_mode_t break_mode)
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{
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{
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gdb_single_step_backup.channel0_used = ubc_get_break_address(0, &gdb_single_step_backup.channel0_addr);
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gdb_single_step_backup.channel0_used = ubc_get_break_address(0, &gdb_single_step_backup.channel0_addr);
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gdb_single_step_backup.channel1_used = ubc_get_break_address(1, &gdb_single_step_backup.channel1_addr);
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gdb_single_step_backup.channel1_used = ubc_get_break_address(1, &gdb_single_step_backup.channel1_addr);
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ubc_disable_channel(0);
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ubc_disable_channel(0);
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ubc_set_breakpoint(1, (void*)cpu_state->reg.pc, UBC_BREAK_AFTER);
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ubc_set_breakpoint(1, (void*)pc, break_mode);
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gdb_single_step_backup.single_stepped = true;
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gdb_single_step_backup.single_stepped = true;
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}
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}
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@ -553,7 +553,7 @@ void gdb_main(gdb_cpu_state_t* cpu_state)
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break;
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break;
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case 's':
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case 's':
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gdb_handle_single_step(cpu_state);
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gdb_handle_single_step(cpu_state->reg.pc, UBC_BREAK_AFTER);
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return;
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return;
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case 'c': // Continue
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case 'c': // Continue
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return;
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return;
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@ -579,20 +579,13 @@ static void gdb_notifier_function(void)
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if (gdb_single_step_backup.single_stepped)
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if (gdb_single_step_backup.single_stepped)
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return;
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return;
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gdb_cpu_state_t fake_state = {};
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gdb_handle_single_step(usb_interrupt_context->spc, UBC_BREAK_AFTER);
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fake_state.reg.pc = usb_interrupt_context->spc;
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gdb_handle_single_step(&fake_state);
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}
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}
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/* TODO : break and let the debugger attempt to fix the issue before panicking
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* in user code
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*/
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static int gdb_panic_handler(uint32_t code)
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static int gdb_panic_handler(uint32_t code)
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{
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{
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// We make sure we currently want to handle TLB misses
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// If we are currently expecting to handle TLB misses
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if (!gdb_tlbh_enable)
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if (gdb_tlbh_enable) {
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return 1;
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// We only handle TLB miss reads (0x040) and writes (0x060)
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// We only handle TLB miss reads (0x040) and writes (0x060)
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if (code != 0x040 && code != 0x060)
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if (code != 0x040 && code != 0x060)
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return 1;
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return 1;
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@ -602,6 +595,19 @@ static int gdb_panic_handler(uint32_t code)
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// We skip the offending instruction and continue
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// We skip the offending instruction and continue
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gint_exc_skip(1);
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gint_exc_skip(1);
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return 0;
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return 0;
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}
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// If we are in user code, let's break
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else if (!ubc_dbh_lock && gdb_state == GDB_STATE_STARTED) {
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// We make sure an other step break is not already set up
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if (gdb_single_step_backup.single_stepped)
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return 1;
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uint32_t spc;
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__asm__("stc spc, %0" : "=r"(spc));
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gdb_handle_single_step(spc, UBC_BREAK_BEFORE);
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return 0;
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}
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return 1;
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}
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}
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int gdb_start(void)
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int gdb_start(void)
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