diff --git a/src/cpg/overclock.c b/src/cpg/overclock.c
index 125615a..396a5cb 100644
--- a/src/cpg/overclock.c
+++ b/src/cpg/overclock.c
@@ -433,6 +433,66 @@ static struct cpg_overclock_setting const settings_fxcg50[5] = {
       .CS5aWCR = 0x000203C1 },
 };
 
+// TODO: These structures are big and many settings overlap. Make it smaller.
+// This is fxcg50[0,1,2,3,3].
+static struct cpg_overclock_setting const settings_fxcg100[5] = {
+    /* CLOCK_SPEED_F1 */
+    { .FLLFRQ  = 0x00004000 + 900,
+      .FRQCR   = 0x0F011112,
+      .CS0BCR  = 0x36DA0400,
+      .CS2BCR  = 0x36DA3400,
+      .CS3BCR  = 0x36DB4400,
+      .CS5aBCR = 0x17DF0400,
+      .CS0WCR  = 0x000003C0,
+      .CS2WCR  = 0x000003C0,
+      .CS3WCR  = 0x000024D1,
+      .CS5aWCR = 0x000203C1 },
+    /* CLOCK_SPEED_F2 */
+    { .FLLFRQ  = 0x00004000 + 900,
+      .FRQCR   = (SH4_PLL_16x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
+      .CS0BCR  = 0x24920400,
+      .CS2BCR  = 0x24923400,
+      .CS3BCR  = 0x24924400,
+      .CS5aBCR = 0x17DF0400,
+      .CS0WCR  = 0x00000340,
+      .CS2WCR  = 0x000003C0,
+      .CS3WCR  = 0x000024D1,
+      .CS5aWCR = 0x000203C1 },
+    /* CLOCK_SPEED_F3 */
+    { .FLLFRQ  = 0x00004000 + 900,
+      .FRQCR  = (SH4_PLL_26x<<24)+(SH4_DIV_4<<20)+(SH4_DIV_8<<12)+(SH4_DIV_8<<8)+SH4_DIV_8,
+      .CS0BCR  = 0x24920400,
+      .CS2BCR  = 0x24923400,
+      .CS3BCR  = 0x24924400,
+      .CS5aBCR = 0x17DF0400,
+      .CS0WCR  = 0x00000240,
+      .CS2WCR  = 0x000003C0,
+      .CS3WCR  = 0x000024D1,
+      .CS5aWCR = 0x000203C1 },
+    /* CLOCK_SPEED_F4 */
+    { .FLLFRQ  = 0x00004000 + 900,
+      .FRQCR  = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
+      .CS0BCR  = 0x24920400,
+      .CS2BCR  = 0x24923400,
+      .CS3BCR  = 0x24924400,
+      .CS5aBCR = 0x17DF0400,
+      .CS0WCR  = 0x000002C0,
+      .CS2WCR  = 0x000003C0,
+      .CS3WCR  = 0x000024D1,
+      .CS5aWCR = 0x000203C1 },
+    /* CLOCK_SPEED_F5 is made identical to CLOCK_SPEED_F4 because clearly the
+       Graph Math+ cannot handle the higher bus speed. */
+    { .FLLFRQ  = 0x00004000 + 900,
+      .FRQCR  = (SH4_PLL_32x<<24)+(SH4_DIV_2<<20)+(SH4_DIV_4<<12)+(SH4_DIV_8<<8)+SH4_DIV_16,
+      .CS0BCR  = 0x24920400,
+      .CS2BCR  = 0x24923400,
+      .CS3BCR  = 0x24924400,
+      .CS5aBCR = 0x17DF0400,
+      .CS0WCR  = 0x000002C0,
+      .CS2WCR  = 0x000003C0,
+      .CS3WCR  = 0x000024D1,
+      .CS5aWCR = 0x000203C1 },
+};
 #endif
 
 static struct cpg_overclock_setting const *get_settings(void)
@@ -451,6 +511,8 @@ static struct cpg_overclock_setting const *get_settings(void)
         return settings_prizm;
     if(gint[HWCALC] == HWCALC_FXCG50)
         return settings_fxcg50;
+    if(gint[HWCALC] == HWCALC_FXCG100)
+        return settings_fxcg100;
 #endif
 
     return NULL;
diff --git a/src/kernel/kernel.c b/src/kernel/kernel.c
index 3541e70..0a08e71 100644
--- a/src/kernel/kernel.c
+++ b/src/kernel/kernel.c
@@ -40,8 +40,8 @@ void *gint_stack_top = NULL;
 /* kinit(): Install and start gint */
 void kinit(void)
 {
-    /* Figure out which CASIOWIN API to use based on the OS type. */
-    #if GINT_OS_CG
+	/* Figure out which CASIOWIN API to use based on the OS type. */
+	#if GINT_OS_CG
 	char *version = (void *)0x80020020;
 	if(!memcmp(version, "01.00", 5))
 		gint_set_CASIOWIN_API(1);