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kernel: mask interrupts during callbacks on SH3!
This change fixes very weird bugs first observed with the RTC, related to IMASK not being updated when an interrupt occurs to avoid re-interruption. On SH4 there is a CPUOPM setting that automatically sets IMASK to the level of the accepted interrupt, which is so exactly what every kernel needs that I can't figure out why this isn't the only behavior. Turns out on SH3 it's not even an option. This commit sets IMASK to 15 when accepting a callback on SH3. This most notably prevents the gray engine from updating the screen so callbacks need to be made very short.
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parent
e617ea63bf
commit
a06213ca11
1 changed files with 20 additions and 5 deletions
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@ -217,13 +217,24 @@ _gint_inth_callback:
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ldc r4, r0_bank
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ldc r4, r0_bank
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ldc r5, r4_bank
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ldc r5, r4_bank
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/* Enable interrupts and go back to user bank. SR.IMASK is already set
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/* Enable interrupts and go back to user bank. On SH4, SR.IMASK is set
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to the level of the current interrupt, which makes sure we can only
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to the level of the current interrupt, which makes sure we can only
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be re-interrupted by something with a higher priority. */
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be re-interrupted by something with a higher priority. */
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stc sr, r0
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stc sr, r1
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mov.l .SR_clear_RB_BL, r1
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mov.l .SR_clear_RB_BL, r0
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and r1, r0
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and r0, r1
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ldc r0, sr
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/* On SH3, set IMASK to 15 to block interrupts while allowing TLB
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misses to be handled. */
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mov.l .gint, r0
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mov.l @r0, r0
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tst #1, r0
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bt .load_sr
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mov.l .SR_set_IMASK, r0
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or r0, r1
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.load_sr:
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ldc r1, sr
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/* We are now in the user bank with r0 and r4 set. Call back. We want
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/* We are now in the user bank with r0 and r4 set. Call back. We want
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to forward the return value to kernel bank, but this bank can be
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to forward the return value to kernel bank, but this bank can be
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@ -256,3 +267,7 @@ _gint_inth_callback:
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.align 4
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.align 4
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.SR_clear_RB_BL:
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.SR_clear_RB_BL:
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.long ~((1 << 29) | (1 << 28))
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.long ~((1 << 29) | (1 << 28))
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.SR_set_IMASK:
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.long (0xf << 4)
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.gint:
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.long _gint
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