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https://git.planet-casio.com/Lephenixnoir/gint.git
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ubc: basic User Break Controller driver
This commit is contained in:
redoste
parent
0bea485f4b
commit
aa0ff7b10b
8 changed files with 407 additions and 52 deletions
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@ -124,6 +124,9 @@ set(SOURCES_COMMON
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src/tmu/inth-tmu.s
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src/tmu/inth-tmu.s
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src/tmu/sleep.c
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src/tmu/sleep.c
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src/tmu/tmu.c
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src/tmu/tmu.c
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# UBC driver
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src/ubc/ubc.c
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src/ubc/ubc.S
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# USB driver
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# USB driver
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src/usb/asyncio.c
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src/usb/asyncio.c
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src/usb/classes/ff-bulk.c
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src/usb/classes/ff-bulk.c
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@ -9,6 +9,8 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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#include <stdint.h>
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/* Error codes for GDB functions */
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/* Error codes for GDB functions */
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enum {
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enum {
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GDB_NO_INTERFACE = -1,
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GDB_NO_INTERFACE = -1,
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@ -16,6 +18,46 @@ enum {
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GDB_USB_ERROR = -3,
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GDB_USB_ERROR = -3,
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};
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};
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/* gdb_cpu_state_t: State of the CPU when breaking
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This struct keep the same register indices as those declared by GDB to allow
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easy R/W without needing a "translation" table.
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See : https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gdb/sh-tdep.c;
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h=c402961b80a0b4589243023ea5362d43f644a9ec;hb=4f3e26ac6ee31f7bc4b04abd
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8bdb944e7f1fc5d2#l327
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*/
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// TODO : Should we expose r*b*, ssr, spc ? are they double-saved when breaking
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// inside an interrupt handler ?
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typedef struct {
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union {
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struct {
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r4;
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uint32_t r5;
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uint32_t r6;
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uint32_t r7;
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uint32_t r8;
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uint32_t r9;
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uint32_t r10;
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uint32_t r11;
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uint32_t r12;
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uint32_t r13;
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uint32_t r14;
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uint32_t r15;
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uint32_t pc;
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uint32_t pr;
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uint32_t gbr;
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uint32_t vbr;
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uint32_t mach;
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uint32_t macl;
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uint32_t sr;
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} reg;
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uint32_t regs[23];
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};
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} gdb_cpu_state_t;
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/* gdb_start(): Start the GDB remote serial protocol server
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/* gdb_start(): Start the GDB remote serial protocol server
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This function will start the GDB remote serial protocol implementation and
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This function will start the GDB remote serial protocol implementation and
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87
include/gint/mpu/ubc.h
Normal file
87
include/gint/mpu/ubc.h
Normal file
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@ -0,0 +1,87 @@
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//---
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// gint:mpu:ubc - User Break Controller
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//---
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#ifndef GINT_MPU_UBC
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#define GINT_MPU_UBC
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/defs/types.h>
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typedef volatile struct
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{
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lword_union(CBR0, /* Match condition setting 0 */
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uint32_t MFE :1; /* Match Flag Enable */
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uint32_t AIE :1; /* ASID Enable */
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uint32_t MFI :6; /* Match Flag Specify */
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uint32_t AIV :8; /* ASID Specify */
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uint32_t :1;
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uint32_t SZ :3; /* Operand Size Select */
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uint32_t :4;
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uint32_t CD :2; /* Bus Select */
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uint32_t ID :2; /* Instruction Fetch / Operand Access Select */
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uint32_t :1;
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uint32_t RW :2; /* Bus Command Select */
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uint32_t CE :1; /* Channel Enable */
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);
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lword_union(CRR0, /* Match operation setting 0 */
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uint32_t :30;
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uint32_t PCB :1; /* PC Break Select */
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uint32_t BIE :1; /* Break Enable */
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);
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uint32_t CAR0; /* Match address setting 0 */
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uint32_t CAMR0; /* Match address mask setting 0 */
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pad(0x10);
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lword_union(CBR1, /* Match condition setting 1 */
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uint32_t MFE :1; /* Match Flag Enable */
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uint32_t AIE :1; /* ASID Enable */
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uint32_t MFI :6; /* Match Flag Specify */
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uint32_t AIV :8; /* ASID Specify */
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uint32_t DBE :1; /* Data Value Enable */
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uint32_t SZ :3; /* Operand Size Select */
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uint32_t ETBE :1; /* Execution Count Value Enable */
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uint32_t :3;
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uint32_t CD :2; /* Bus Select */
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uint32_t ID :2; /* Instruction Fetch / Operand Access Select */
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uint32_t :1;
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uint32_t RW :2; /* Bus Command Select */
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uint32_t CE :1; /* Channel Enable */
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);
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lword_union(CRR1, /* Match operation setting 1 */
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uint32_t :30;
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uint32_t PCB :1; /* PC Break Select */
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uint32_t BIE :1; /* Break Enable */
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);
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uint32_t CAR1; /* Match address setting 1 */
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uint32_t CAMR1; /* Match address mask setting 1 */
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uint32_t CDR1; /* Match data setting 1 */
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uint32_t CDMR1; /* Match data mask setting 1 */
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lword_union(CETR1, /* Execution count break 1 */
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uint32_t :20;
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uint32_t CET :12; /* Execution Count */
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);
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pad(0x5c4);
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lword_union(CCMFR, /* Channel match flag */
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uint32_t :30;
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uint32_t MF1 :1; /* Channel 1 Condition Match Flag */
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uint32_t MF0 :1; /* Channel 0 Condition Match Flag */
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);
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pad(0x1c);
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lword_union(CBCR, /* Break control */
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uint32_t :31;
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uint32_t UBDE :1; /* User Break Debugging Support Function Enable */
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);
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} GPACKED(4) sh7305_ubc_t;
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#define SH7305_UBC (*(sh7305_ubc_t *)0xff200000)
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_MPU_UBC */
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54
include/gint/ubc.h
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54
include/gint/ubc.h
Normal file
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@ -0,0 +1,54 @@
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//---
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// gint:ubc - User Break Controller driver
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//---
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#ifndef GINT_UBC
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#define GINT_UBC
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <gint/gdb.h>
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/* Read and write the DBR register */
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void ubc_setDBR(void* DBR);
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void* ubc_getDBR(void);
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/* ubc_dbh(): Low level UBC debug handler
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The handler will backup the current CPU state and call ubc_debug_handler(). */
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void ubc_dbh(void);
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/* ubc_debug_handler(): C level UBC debug handler
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The execution will be redirected to the handler set by the user or the add-in
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will panic in case no handler has been set. */
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void ubc_debug_handler(gdb_cpu_state_t* cpu_state);
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/* ubc_set_debug_handler(): Set user debug handler
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Set a custom debug handler that will be called when a break condition from
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the UBC is reached. */
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void ubc_set_debug_handler(void (*h)(gdb_cpu_state_t*));
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/* UBC Breakpoint types */
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typedef enum {
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UBC_BREAK_BEFORE, /* Break before the instruction is executed */
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UBC_BREAK_AFTER, /* Break after the instruction is executed :
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at this point PC will point to the next instruction. */
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} ubc_break_mode_t;
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/* ubc_set_breakpoint(): Set a breakpoint in a UBC channel and enable it
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Return false when an invalid channel number is provided, true if the
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breakpoint was correctly set up. */
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bool ubc_set_breakpoint(int channel, void* break_address, ubc_break_mode_t break_mode);
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/* ubc_get_break_address(): Get a breakpoint address if it's enabled
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If the channel is disabled the function will return false and *break_address
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will not be updated. */
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bool ubc_get_break_address(int channel, void** break_address);
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/* ubc_disable_channel(): Disable a UBC channel
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Return true on success. If an invalid channel number is provided, it will
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return false. */
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bool ubc_disable_channel(int channel);
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#ifdef __cplusplus
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}
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#endif
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#endif /* GINT_UBC */
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@ -8,8 +8,6 @@
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <string.h>
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#include "gdb_private.h"
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static void gdb_hexlify(char* output_string, const uint8_t* input_buffer, size_t input_size)
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static void gdb_hexlify(char* output_string, const uint8_t* input_buffer, size_t input_size)
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{
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{
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const char* hex = "0123456789ABCDEF";
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const char* hex = "0123456789ABCDEF";
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@ -1,50 +0,0 @@
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//---
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// gint:gdb:gdb-private - Private definitions for the GDB implementation
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//---
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#ifndef GINT_GDB_PRIVATE
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#define GINT_GDB_PRIVATE
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#include <stdint.h>
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/* gdb_cpu_state_t: State of the CPU when breaking
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This struct keep the same register indices as those declared by GDB to allow
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easy R/W without needing a "translation" table.
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See : https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gdb/sh-tdep.c;
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h=c402961b80a0b4589243023ea5362d43f644a9ec;hb=4f3e26ac6ee31f7bc4b04abd
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8bdb944e7f1fc5d2#l327
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*/
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// TODO : Should we expose r*b*, ssr, spc ? are they double-saved when breaking
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// inside an interrupt handler ?
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typedef struct {
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union {
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struct {
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r4;
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uint32_t r5;
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uint32_t r6;
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uint32_t r7;
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uint32_t r8;
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uint32_t r9;
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uint32_t r10;
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uint32_t r11;
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uint32_t r12;
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uint32_t r13;
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uint32_t r14;
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uint32_t r15;
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uint32_t pc;
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uint32_t pr;
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uint32_t gbr;
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uint32_t vbr;
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uint32_t mach;
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uint32_t macl;
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uint32_t sr;
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} reg;
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uint32_t regs[23];
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};
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} gdb_cpu_state_t;
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#endif /* GINT_GDB_PRIVATE */
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89
src/ubc/ubc.S
Normal file
89
src/ubc/ubc.S
Normal file
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@ -0,0 +1,89 @@
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.global _ubc_setDBR
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.global _ubc_getDBR
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.text
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_ubc_setDBR:
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ldc r4, dbr
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rts
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nop
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_ubc_getDBR:
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stc dbr, r0
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rts
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nop
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.global _ubc_dbh
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_ubc_dbh:
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/* We backup registers in the correct order to build gdb_cpu_state_t */
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stc.l ssr, @-r15
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sts.l macl, @-r15
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sts.l mach, @-r15
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stc.l vbr, @-r15
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stc.l gbr, @-r15
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sts.l pr, @-r15
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stc.l spc, @-r15
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stc.l sgr, @-r15
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mov.l r14, @-r15
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mov.l r13, @-r15
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mov.l r12, @-r15
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mov.l r11, @-r15
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mov.l r10, @-r15
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mov.l r9, @-r15
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mov.l r8, @-r15
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stc.l R7_BANK, @-r15
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stc.l R6_BANK, @-r15
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stc.l R5_BANK, @-r15
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stc.l R4_BANK, @-r15
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stc.l R3_BANK, @-r15
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stc.l R2_BANK, @-r15
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stc.l R1_BANK, @-r15
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stc.l R0_BANK, @-r15
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/* Enable interrupts and switch register bank
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Original SR is kept in r8 */
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stc sr, r8
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mov r8, r1
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mov.l .sr_mask, r0
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and r0, r1
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ldc r1, sr
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mov r15, r4
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mov.l .handler, r0
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jsr @r0
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nop
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/* Restore original SR to access the correct register bank */
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ldc r8, sr
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ldc.l @r15+, R0_BANK
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ldc.l @r15+, R1_BANK
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ldc.l @r15+, R2_BANK
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ldc.l @r15+, R3_BANK
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ldc.l @r15+, R4_BANK
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ldc.l @r15+, R5_BANK
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ldc.l @r15+, R6_BANK
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ldc.l @r15+, R7_BANK
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mov.l @r15+, r8
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mov.l @r15+, r9
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mov.l @r15+, r10
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mov.l @r15+, r11
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mov.l @r15+, r12
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mov.l @r15+, r13
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mov.l @r15+, r14
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ldc.l @r15+, sgr
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ldc.l @r15+, spc
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lds.l @r15+, pr
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ldc.l @r15+, gbr
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ldc.l @r15+, vbr
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lds.l @r15+, mach
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lds.l @r15+, macl
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ldc.l @r15+, ssr
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rte
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nop
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.align 4
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.handler: .long _ubc_debug_handler
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.sr_mask: .long ~0x300000f0 /* IMASK = 0 : mask no interrupts
|
||||||
|
BL = 0 : do not block interrupts
|
||||||
|
RB = 0 : use register BANK0
|
||||||
|
*/
|
||||||
132
src/ubc/ubc.c
Normal file
132
src/ubc/ubc.c
Normal file
|
|
@ -0,0 +1,132 @@
|
||||||
|
#include <gint/drivers.h>
|
||||||
|
#include <gint/exc.h>
|
||||||
|
#include <gint/gdb.h>
|
||||||
|
#include <gint/mpu/power.h>
|
||||||
|
#include <gint/mpu/ubc.h>
|
||||||
|
#include <gint/ubc.h>
|
||||||
|
|
||||||
|
#define UBC SH7305_UBC
|
||||||
|
#define POWER SH7305_POWER
|
||||||
|
|
||||||
|
static bool hpowered(void)
|
||||||
|
{
|
||||||
|
return POWER.MSTPCR0.UDB == 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void hpoweron(void)
|
||||||
|
{
|
||||||
|
// Power on the UBC via MSTPCR0
|
||||||
|
POWER.MSTPCR0.UDB = 0;
|
||||||
|
|
||||||
|
// Set the DBR register
|
||||||
|
ubc_setDBR(ubc_dbh);
|
||||||
|
|
||||||
|
// Disable break channel 0 and 1
|
||||||
|
UBC.CBR0.CE = 0;
|
||||||
|
UBC.CBR1.CE = 0;
|
||||||
|
|
||||||
|
// Enable user break debugging support (i.e. usage of the DBR register)
|
||||||
|
UBC.CBCR.UBDE = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void hpoweroff(void)
|
||||||
|
{
|
||||||
|
POWER.MSTPCR0.UDB = 1;
|
||||||
|
|
||||||
|
UBC.CBR0.CE = 0;
|
||||||
|
UBC.CBR1.CE = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define UBC_BREAK_CHANNEL(CBR, CRR, CAR, CAMR) do { \
|
||||||
|
UBC.CBR.MFE = 0; /* Don't include Match Flag in match condition */ \
|
||||||
|
UBC.CBR.AIE = 0; /* Don't include ASID check in match condition */ \
|
||||||
|
UBC.CBR.MFI = 0; /* Default value of MFI is reserved, make it legal */ \
|
||||||
|
UBC.CBR.SZ = 0; /* Match on any operand size */ \
|
||||||
|
UBC.CBR.CD = 0; /* Match on operand bus access */ \
|
||||||
|
UBC.CBR.ID = 1; /* Match on instruction fetch */ \
|
||||||
|
UBC.CBR.RW = 1; /* Match on read cycle */ \
|
||||||
|
\
|
||||||
|
UBC.CRR.PCB = pcb; /* Set PC break {before,after} instruction execution */ \
|
||||||
|
UBC.CRR.BIE = 1; /* Break when channel matches */ \
|
||||||
|
\
|
||||||
|
UBC.CAR = (uint32_t)break_address; /* Match address */ \
|
||||||
|
UBC.CAMR = 0; /* Match mask (0 bits are included) */ \
|
||||||
|
UBC.CBR.CE = 1; /* Enable channel */ \
|
||||||
|
} while (0)
|
||||||
|
bool ubc_set_breakpoint(int channel, void* break_address, ubc_break_mode_t break_mode)
|
||||||
|
{
|
||||||
|
if (!hpowered())
|
||||||
|
hpoweron();
|
||||||
|
|
||||||
|
uint32_t pcb = break_mode == UBC_BREAK_AFTER ? 1 : 0;
|
||||||
|
if (channel == 0) {
|
||||||
|
UBC_BREAK_CHANNEL(CBR0, CRR0, CAR0, CAMR0);
|
||||||
|
return true;
|
||||||
|
} else if (channel == 1) {
|
||||||
|
UBC_BREAK_CHANNEL(CBR1, CRR1, CAR1, CAMR1);
|
||||||
|
return true;
|
||||||
|
} else {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#undef UBC_BREAK_CHANNEL
|
||||||
|
|
||||||
|
bool ubc_get_break_address(int channel, void** break_address)
|
||||||
|
{
|
||||||
|
if (!hpowered())
|
||||||
|
hpoweron();
|
||||||
|
|
||||||
|
if (channel == 0 && UBC.CBR0.CE) {
|
||||||
|
*break_address = (void*) UBC.CAR0;
|
||||||
|
return true;
|
||||||
|
} else if (channel == 1 && UBC.CBR1.CE) {
|
||||||
|
*break_address = (void*) UBC.CAR1;
|
||||||
|
return true;
|
||||||
|
} else {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
bool ubc_disable_channel(int channel)
|
||||||
|
{
|
||||||
|
if (!hpowered())
|
||||||
|
hpoweron();
|
||||||
|
|
||||||
|
if (channel == 0) {
|
||||||
|
UBC.CBR0.CE = 0;
|
||||||
|
return true;
|
||||||
|
} else if (channel == 1) {
|
||||||
|
UBC.CBR1.CE = 0;
|
||||||
|
return true;
|
||||||
|
} else {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void (*ubc_application_debug_handler)(gdb_cpu_state_t*) = NULL;
|
||||||
|
void ubc_debug_handler(gdb_cpu_state_t* cpu_state)
|
||||||
|
{
|
||||||
|
// Clear match flags
|
||||||
|
UBC.CCMFR.lword = 0;
|
||||||
|
|
||||||
|
if (ubc_application_debug_handler != NULL) {
|
||||||
|
ubc_application_debug_handler(cpu_state);
|
||||||
|
} else {
|
||||||
|
// TODO : Should we add a custom panic code ?
|
||||||
|
gint_panic(-1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// TODO : Should we use the struct designed for GDB or make it more generic ?
|
||||||
|
void ubc_set_debug_handler(void (*h)(gdb_cpu_state_t*)) {
|
||||||
|
ubc_application_debug_handler = h;
|
||||||
|
}
|
||||||
|
|
||||||
|
gint_driver_t drv_ubc = {
|
||||||
|
.name = "UBC",
|
||||||
|
.hpowered = hpowered,
|
||||||
|
.hpoweron = hpoweron,
|
||||||
|
.hpoweroff = hpoweroff,
|
||||||
|
.flags = GINT_DRV_SHARED,
|
||||||
|
};
|
||||||
|
GINT_DECLARE_DRIVER(30, drv_ubc);
|
||||||
Loading…
Reference in a new issue