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https://git.planet-casio.com/Lephenixnoir/gint.git
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clock: add overclock support on fx-CG 10/20/50
This commit is contained in:
Lephe
parent
c2ff07427b
commit
b942bc5d19
9 changed files with 351 additions and 9 deletions
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@ -24,6 +24,7 @@ configure_file(include/gint/config.h.in include/gint/config.h)
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set(SOURCES_COMMON
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set(SOURCES_COMMON
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# Clock Pulse Generator driver
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# Clock Pulse Generator driver
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src/cpg/cpg.c
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src/cpg/cpg.c
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src/cpg/overclock.c
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# CPU driver
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# CPU driver
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src/cpu/atomic.c
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src/cpu/atomic.c
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src/cpu/cpu.c
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src/cpu/cpu.c
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6
TODO
6
TODO
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@ -1,8 +1,5 @@
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gint 2.8 image things:
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* Design the new image formats, inspired from libimg
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* Replace the [profile] attribute with [format]
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Extensions on existing code:
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Extensions on existing code:
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* clock: mono support
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* usb: add PC->calc reading, and interrupt pipes
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* usb: add PC->calc reading, and interrupt pipes
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* fs: support RAM files
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* fs: support RAM files
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* fs: support USB streams as generic file descriptors
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* fs: support USB streams as generic file descriptors
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@ -19,7 +16,6 @@ Extensions on existing code:
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* core: run destructors when a task-switch results in leaving the app
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* core: run destructors when a task-switch results in leaving the app
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Future directions:
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Future directions:
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* Integrate overclock management
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* Audio playback using TSWilliamson's libsnd method
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* Audio playback using TSWilliamson's libsnd method
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* Serial communication
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* Serial communication
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* Make fx9860g projects work out of the box on fxcg50
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* Make fx9860g projects work out of the box on fxcg50
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@ -61,7 +61,69 @@ void cpg_compute_freq(void);
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// Overclock
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// Overclock
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//---
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//---
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/* TODO: All overclock */
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/* The following enumerations define the clock speed settings supported by
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gint. These are always the settings from Ftune/Ptune, which are the most
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widely tested and gint treats as the standard. */
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enum {
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/* Combinations of hardware settings that are none of Ftune's levels */
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CLOCK_SPEED_UNKNOWN = 0,
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/* Ftune's 5 default overclock levels. The main settings are listed below,
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thoug many more are involved.
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On SH4 fx-9860G-likr:
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(Not supported yet)
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On the fx G-III series:
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(Not supported yet)
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On fx-CG 10/20:
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F1: CPU @ 58 MHz, BFC @ 29 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [Improved memory speed]
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F3: CPU @ 118 MHz, BFC @ 58 MHz [Faster than F2]
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F4: CPU @ 118 MHz, BFC @ 118 MHz [Fastest bus option]
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F5: CPU @ 191 MHz, BFC @ 94 MHz [Fastest CPU option]
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On fx-CG 50:
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F1: CPU @ 116 MHz, BFC @ 58 MHz [Default speed]
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F2: CPU @ 58 MHz, BFC @ 29 MHz [Clearly slower: F2 < F3 < F1]
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F3: CPU @ 94 MHz, BFC @ 47 MHz [Clearly slower: F2 < F3 < F1]
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F4: CPU @ 232 MHz, BFC @ 58 MHz [Fastest CPU option]
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F5: CPU @ 189 MHz, BFC @ 94 MHz [Fastest bus option] */
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CLOCK_SPEED_F1 = 1,
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CLOCK_SPEED_F2 = 2,
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CLOCK_SPEED_F3 = 3,
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CLOCK_SPEED_F4 = 4,
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CLOCK_SPEED_F5 = 5,
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/* The default clock speed is always Ftune's F1 */
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CLOCK_SPEED_DEFAULT = CLOCK_SPEED_F1,
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};
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#ifdef FXCG50
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/* clock_get_speed(): Determine the current clock speed
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This function compares the current hardware state with the settings for each
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speed level and returns the current one. If the hardware state does not
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correspond to any of Ftune's settings, CLOCK_SPEED_UNKNOWN is returned. */
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int clock_get_speed(void);
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/* clock_set_speed(): Set the current clock speed
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This function sets the clock speed to the desired level. This is "the
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overclock function", although depending on the model or settings it is also
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the downclocking function.
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The process of changing clock speeds is non-trivial, requires waiting for
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the DMA to finish its work and slightly affects running timers. You should
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avoid changing the clock speed constantly if not necessary. If this function
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detects that the desired clock speed is already in use, it returns without
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performing any change.
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Currently the clock speed is not reset during a world switch nor when
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leaving the add-in. */
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void clock_set_speed(int speed);
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#endif
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//---
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//---
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// Sleep functions
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// Sleep functions
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@ -41,6 +41,13 @@ int gint_world_switch(gint_call_t function);
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__attribute__((deprecated("Use gint_world_switch() instead")))
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__attribute__((deprecated("Use gint_world_switch() instead")))
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void gint_switch(void (*function)(void));
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void gint_switch(void (*function)(void));
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/* gint_world_sync(): Synchronize asynchronous drivers
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This function waits for asynchronous tasks to complete by unbinding all
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drivers. This is useful in certain hardware operations while remaining in
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gint. */
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void gint_world_sync(void);
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/* gint_osmenu(): Call the calculator's main menu
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/* gint_osmenu(): Call the calculator's main menu
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This function safely invokes the calculator's main menu with gint_switch().
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This function safely invokes the calculator's main menu with gint_switch().
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@ -485,7 +485,7 @@ image_t *image_vflip_alloc(image_t const *src);
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top-left corner of the full output is actually rendered.
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top-left corner of the full output is actually rendered.
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Formats: RGB16, P8
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Formats: RGB16, P8
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Size requirement: none (clipping through image_linear_opt settings)
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Size requirement: none (clipping is performed)
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Supports in-place: No */
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Supports in-place: No */
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struct image_linear_map {
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struct image_linear_map {
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@ -142,8 +142,6 @@ typedef volatile struct
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} GPACKED(4) sh7305_bsc_t;
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} GPACKED(4) sh7305_bsc_t;
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#define SH7305_BSC (*(sh7305_bsc_t *)0xfec10000)
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#define SH7305_BSC (*(sh7305_bsc_t *)0xfec10000)
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#define SH7305_BSC_SDMR2 (*(uint8_t *)0xfec14000)
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#define SH7305_BSC_SDMR3 (*(uint8_t *)0xfec15000)
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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241
src/cpg/overclock.c
Normal file
241
src/cpg/overclock.c
Normal file
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@ -0,0 +1,241 @@
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//---
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// gint:cpg:overclock - Clock speed control
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//
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// Most of the data in this file has been reused from Sentaro21's Ftune and
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// Ptune utilities, which have long been the standard for overclocking CASIO
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// calculators.
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// See: http://pm.matrix.jp/ftune2e.html
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//
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// SlyVTT also contributed early testing on both the fx-CG 10/20 and fx-CG 50.
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//---
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#include <gint/clock.h>
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#include <gint/hardware.h>
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#include <gint/gint.h>
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#include <gint/mpu/cpg.h>
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#include <gint/mpu/bsc.h>
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#ifdef FXCG50
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#define CPG SH7305_CPG
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#define BSC SH7305_BSC
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#define PLL_32x 0b011111
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#define PLL_26x 0b011001
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#define PLL_16x 0b001111
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#define DIV_2 0
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#define DIV_4 1
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#define DIV_8 2
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#define DIV_16 3
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#define DIV_32 4
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#define WAIT18 0b1011
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struct overclock_setting
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{
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uint32_t FLLFRQ, FRQCR;
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uint32_t CS0BCR, CS2BCR, CS3BCR, CS5aBCR;
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uint32_t CS0WCR, CS2WCR, CS3WCR, CS5aWCR;
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};
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#define SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
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#define SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
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static struct overclock_setting settings_cg50[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F011112,
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.CS0BCR = 0x36DA0400,
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.CS2BCR = 0x36DA3400,
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.CS3BCR = 0x36DB4400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x000003C0,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_16x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000340,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000240,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_8<<8)+DIV_16,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x000002C0,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_8,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS3BCR = 0x24924400,
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.CS5aBCR = 0x17DF0400,
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.CS0WCR = 0x00000440,
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.CS2WCR = 0x000003C0,
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.CS3WCR = 0x000024D1,
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.CS5aWCR = 0x000203C1 },
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};
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static struct overclock_setting settings_cg20[5] = {
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/* CLOCK_SPEED_F1 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = 0x0F102203,
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.CS0BCR = 0x24920400,
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.CS2BCR = 0x24923400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000001C0,
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.CS2WCR = 0x00000140,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F2 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_8<<20)+(DIV_16<<12)+(DIV_16<<8)+DIV_32,
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.CS0BCR = 0x04900400,
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.CS2BCR = 0x04903400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x00000140,
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.CS2WCR = 0x000100C0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F3 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_8<<12)+(DIV_8<<8)+DIV_32,
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.CS0BCR = 0x24900400,
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.CS2BCR = 0x04903400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000002C0,
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.CS2WCR = 0x000201C0,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F4 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_32x<<24)+(DIV_4<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_32,
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.CS0BCR = 0x44900400,
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.CS2BCR = 0x04903400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x00000440,
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.CS2WCR = 0x00040340,
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.CS5aWCR = 0x00010240 },
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/* CLOCK_SPEED_F5 */
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{ .FLLFRQ = 0x00004000 + 900,
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.FRQCR = (PLL_26x<<24)+(DIV_2<<20)+(DIV_4<<12)+(DIV_4<<8)+DIV_16,
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.CS0BCR = 0x34900400,
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.CS2BCR = 0x04903400,
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.CS5aBCR = 0x15140400,
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.CS0WCR = 0x000003C0,
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.CS2WCR = 0x000402C0,
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.CS5aWCR = 0x00010240 },
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};
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static struct overclock_setting *get_settings(void)
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{
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if(gint[HWCALC] == HWCALC_FXCG50)
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return settings_cg50;
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if(gint[HWCALC] == HWCALC_PRIZM)
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return settings_cg20;
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return NULL;
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}
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int clock_get_speed(void)
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{
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struct overclock_setting *settings = get_settings();
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if(!settings)
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return CLOCK_SPEED_UNKNOWN;
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for(int i = 0; i < 5; i++) {
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struct overclock_setting *s = &settings[i];
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if(CPG.FLLFRQ.lword == s->FLLFRQ
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&& CPG.FRQCR.lword == s->FRQCR
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&& BSC.CS0BCR.lword == s->CS0BCR
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&& BSC.CS2BCR.lword == s->CS2BCR
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&& BSC.CS3BCR.lword == s->CS3BCR
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&& BSC.CS5ABCR.lword == s->CS5aBCR
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&& BSC.CS0WCR.lword == s->CS0WCR
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&& BSC.CS2WCR.lword == s->CS2WCR
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&& BSC.CS3WCR.lword == s->CS3WCR
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&& BSC.CS5AWCR.lword == s->CS5aWCR)
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return CLOCK_SPEED_F1 + i;
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}
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return CLOCK_SPEED_UNKNOWN;
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}
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void clock_set_speed(int level)
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{
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if(level < CLOCK_SPEED_F1 || level > CLOCK_SPEED_F5)
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return;
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if(clock_get_speed() == level)
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return;
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struct overclock_setting *settings = get_settings();
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if(!settings)
|
||||||
|
return;
|
||||||
|
|
||||||
|
struct overclock_setting *s = &settings[level - CLOCK_SPEED_F1];
|
||||||
|
uint32_t old_Pphi = clock_freq()->Pphi_f;
|
||||||
|
|
||||||
|
/* Wait for asynchronous tasks to complete */
|
||||||
|
gint_world_sync();
|
||||||
|
|
||||||
|
/* Disable interrupts during the change */
|
||||||
|
cpu_atomic_start();
|
||||||
|
|
||||||
|
/* Set the clock settings */
|
||||||
|
|
||||||
|
BSC.CS0WCR.WR = WAIT18;
|
||||||
|
|
||||||
|
CPG.FLLFRQ.lword = s->FLLFRQ;
|
||||||
|
CPG.FRQCR.lword = s->FRQCR;
|
||||||
|
CPG.FRQCR.KICK = 1;
|
||||||
|
while(CPG.LSTATS != 0) {}
|
||||||
|
|
||||||
|
BSC.CS0BCR.lword = s->CS0BCR;
|
||||||
|
BSC.CS0WCR.lword = s->CS0WCR;
|
||||||
|
BSC.CS2BCR.lword = s->CS2BCR;
|
||||||
|
BSC.CS2WCR.lword = s->CS2WCR;
|
||||||
|
|
||||||
|
if(gint[HWCALC] == HWCALC_FXCG50) {
|
||||||
|
BSC.CS3BCR.lword = s->CS3BCR;
|
||||||
|
BSC.CS3WCR.lword = s->CS3WCR;
|
||||||
|
|
||||||
|
if(BSC.CS3WCR.A3CL == 1)
|
||||||
|
*SDMR3_CL2 = 0;
|
||||||
|
else
|
||||||
|
*SDMR3_CL3 = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
BSC.CS5ABCR.lword = s->CS5aBCR;
|
||||||
|
BSC.CS5AWCR.lword = s->CS5aWCR;
|
||||||
|
|
||||||
|
/* Determine the change in frequency for Pϕ and recompute CPG data */
|
||||||
|
cpg_compute_freq();
|
||||||
|
uint32_t new_Pphi = clock_freq()->Pphi_f;
|
||||||
|
|
||||||
|
/* Update timers' TCNT and TCOR to match the new clock speed */
|
||||||
|
void timer_rescale(uint32_t old_Pphi, uint32_t new_Pphi);
|
||||||
|
timer_rescale(old_Pphi, new_Pphi);
|
||||||
|
|
||||||
|
cpu_atomic_end();
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -38,6 +38,20 @@ void gint_world_free(gint_world_t world)
|
||||||
free(world);
|
free(world);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
//---
|
||||||
|
// Synchronization
|
||||||
|
//---
|
||||||
|
|
||||||
|
void gint_world_sync(void)
|
||||||
|
{
|
||||||
|
/* Unbind all drivers, which waits for async tasks to complete */
|
||||||
|
for(int i = gint_driver_count() - 1; i >= 0; i--)
|
||||||
|
{
|
||||||
|
gint_driver_t *d = &gint_drivers[i];
|
||||||
|
if(d->unbind) d->unbind();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
//---
|
//---
|
||||||
// World switch with driver state saves
|
// World switch with driver state saves
|
||||||
//---
|
//---
|
||||||
|
|
|
||||||
|
|
@ -260,6 +260,29 @@ void timer_spinwait(int id)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
//---
|
||||||
|
// Overclock adjustment
|
||||||
|
//---
|
||||||
|
|
||||||
|
void timer_rescale(uint32_t old_Pphi, uint32_t new_Pphi_0)
|
||||||
|
{
|
||||||
|
uint64_t new_Pphi = new_Pphi_0;
|
||||||
|
|
||||||
|
for(int id = 0; id < 3; id++)
|
||||||
|
{
|
||||||
|
tmu_t *T = &TMU[id];
|
||||||
|
/* Skip timers that are not running */
|
||||||
|
if(T->TCNT == 0xffffffff && T->TCOR == 0xffffffff)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* For libprof: keep timers with max TCOR as they are */
|
||||||
|
if(T->TCOR != 0xffffffff) {
|
||||||
|
T->TCOR = ((uint64_t)T->TCOR * new_Pphi) / old_Pphi;
|
||||||
|
}
|
||||||
|
T->TCNT = ((uint64_t)T->TCNT * new_Pphi) / old_Pphi;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
//---
|
//---
|
||||||
// Deprecated API
|
// Deprecated API
|
||||||
//---
|
//---
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue