kernel: mask interrupts during callbacks on fx-CG Manager

The fx-CG Manager holds but ignores the CPUOPM.INTMU bit, which means
that we have to mask interrupts as on SH3.

include/gint/hardware.h

@@ -14,15 +14,24 @@
 #ifndef GINT_HARDWARE
 #define GINT_HARDWARE
 
+/* For compatibility with ASM, include the following bits only in C code */
+#ifndef CPP_ASM
+
 #include <gint/defs/types.h>
 
 /* Most of the information here is going to be stored in (key, value) pairs for
    predetermined keys and 32-bits values that are often integers or a set of
    flags. The data will be filled by gint or its drivers. */
-
 #define HW_KEYS 16
 extern uint32_t gint[HW_KEYS];
 
+/* hw_detect(): Basic hardware detection
+   This function probes the hardware and fills in the HWMPU, HWCPUVR and
+   HWCPUPR fields. */
+void hw_detect(void);
+
+#endif /* CPP_ASM */
+
 /* MPU detection macros, with a faster version on fx-CG 50 and a generic
    dual-platform version for libraries.
    Warning: this macro is also used hardcoded in exch.s. */
@@ -37,11 +46,6 @@ extern uint32_t gint[HW_KEYS];
 #define isSH4() 1
 #endif
 
-/* hw_detect(): Basic hardware detection
-   This function probes the hardware and fills in the HWMPU, HWCPUVR and
-   HWCPUPR fields. */
-void hw_detect(void);
-
 /* This bit should be set in all data longwords except HWMPU, HWCPUVR, HWCPUPR
    and HWCALC which are guaranteed to always be loaded. If not set then the
    information must be treated as invalid. */
@@ -54,7 +58,7 @@ void hw_detect(void);
 #define HWMPU    0    /* MPU type */
 #define HWCPUVR  1    /* CPU Version Register */
 #define HWCPUPR  2    /* CPU Product Register */
-#define HWCALC   3    /* Calculator model */
+#define HWCALC   3    /* Calculator model, hardcoded in kernel/inth.S */
 #define HWRAM    4    /* Amount of RAM */
 #define HWROM    5    /* Amount of ROM */
 #define HWURAM   6    /* Userspace RAM */
@@ -94,7 +98,7 @@ void hw_detect(void);
 #define HWCALC_PRIZM         4
 /* fx-CG 50, a late extension to the Prizm family */
 #define HWCALC_FXCG50        5
-/* fx-CG 50 emulator */
+/* fx-CG 50 emulator, hardcoded in kernel/inth.S */
 #define HWCALC_FXCG_MANAGER  6
 
 /*

make/Makefile

@@ -26,10 +26,11 @@ machine ?= -m4-nofpu -mb
 endif
 
 # Compiler flags, assembler flags, dependency generation, archiving
+inc     := -I ../include
 cflags  := $(machine) -ffreestanding -nostdlib -Wall -Wextra -std=c11 -Os \
-           -fstrict-volatile-bitfields -I ../include $(CONFIG.MACROS) \
+           -fstrict-volatile-bitfields $(inc) $(CONFIG.MACROS) \
            $(CONFIG.CFLAGS)
-sflags  := $(CONFIG.MACROS)
+sflags  := $(inc) $(CONFIG.MACROS)
 dflags   = -MMD -MT $@ -MF $(@:.o=.d) -MP
 arflags :=
 

src/core/inth.S

@@ -5,6 +5,9 @@
 **	blocks depending on its configuration.
 */
 
+#define CPP_ASM
+#include <gint/hardware.h>
+
 .global _gint_inth_7305
 
 #ifdef FX9860G
@@ -224,12 +227,21 @@ _gint_inth_callback:
 	mov.l	.SR_clear_RB_BL, r0
 	and	r0, r1
 
-	/* On SH3, set IMASK to 15 to block interrupts while allowing TLB
-	   misses to be handled. */
-	mov.l	.gint, r0
-	mov.l	@r0, r0
+	/* On SH3 the CPUOPM.INTMU bit is not supported, and on the fx-CG
+	   emulator, it is outright ignored. In these situations, set IMASK to
+	   15 to block interrupts while allowing TLB misses to be handled. */
+	mov.l	.gint, r2
+	mov.l	@r2, r0
 	tst	#1, r0
-	bt	.load_sr
+	bf	.set_imask
+	mov.l	@(4*HWCALC,r2), r0
+	cmp/eq	#HWCALC_FXCG_MANAGER, r0
+	bt	.set_imask
+
+	bra	.load_sr
+	nop
+
+.set_imask:
 	mov.l	.SR_set_IMASK, r0
 	or	r0, r1