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mpu: rename FRQCRA into FRQCR

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Lephe 2022-04-12 16:23:18 +01:00
parent b10c065abe
commit fdadb0dd71
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2 changed files with 5 additions and 5 deletions
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2
include/gint/mpu/cpg.h
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@ -47,7 +47,7 @@ typedef volatile struct
documentation. */ documentation. */
typedef volatile struct typedef volatile struct
{ {
lword_union(FRQCRA, lword_union(FRQCR,
uint32_t KICK :1; /* Flush FRQCRA modifications */ uint32_t KICK :1; /* Flush FRQCRA modifications */
uint32_t :1; uint32_t :1;
uint32_t STC :6; /* PLL multiplication [*] */ uint32_t STC :6; /* PLL multiplication [*] */

8
src/cpg/cpg.c
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@ -82,7 +82,7 @@ static void sh7305_probe(void)
{ {
/* The meaning of the PLL setting on SH7305 differs from the /* The meaning of the PLL setting on SH7305 differs from the
documentation of SH7224; the value must not be doubled. */ documentation of SH7224; the value must not be doubled. */
int pll = CPG.FRQCRA.STC + 1; int pll = CPG.FRQCR.STC + 1;
freq.PLL = pll; freq.PLL = pll;
/* The FLL ratio is the value of the setting, halved if SELXM=1 */ /* The FLL ratio is the value of the setting, halved if SELXM=1 */
@ -93,9 +93,9 @@ static void sh7305_probe(void)
/* On SH7724, the divider ratio is given by 1 / (setting + 1), but on /* On SH7724, the divider ratio is given by 1 / (setting + 1), but on
the SH7305 it is 1 / (2^setting + 1). */ the SH7305 it is 1 / (2^setting + 1). */
int divb = CPG.FRQCRA.BFC; int divb = CPG.FRQCR.BFC;
int divi = CPG.FRQCRA.IFC; int divi = CPG.FRQCR.IFC;
int divp = CPG.FRQCRA.P1FC; int divp = CPG.FRQCR.P1FC;
freq.Bphi_div = 1 << (divb + 1); freq.Bphi_div = 1 << (divb + 1);
freq.Iphi_div = 1 << (divi + 1); freq.Iphi_div = 1 << (divi + 1);