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https://git.planet-casio.com/Lephenixnoir/gint.git
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2b1f408cb4
I have recenty discovered that the so-called "rram" section used by gint to store its VBR space and a couple memory structures gets overwritten when returning to the main menu. It is thus necessary to get rid of it and store that data somewhere else. My current lead is to have it at the start of the static RAM by querying its address in the TLB. However, the static RAM is very small on SH3 (8k) so the VBR must be made more compact. This change elaborates the event code translation scheme used on SH3 to emulate SH4 event codes. It is now used to translate the event codes to a gint-specific VBR layout that leaves no gaps and thus reduces the size of the VBR space. The gint_inthandler() method has to be modified for every new SH3 interrupt to maintain this scheme.
227 lines
6.2 KiB
ArmAsm
227 lines
6.2 KiB
ArmAsm
/*
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** gint:tmu:inth - Interrupt handlers for the timer units
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** Perhaps the most technical of my interrupt handlers. They implement a
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** simple kind of interrupt handler communication by letting the control flow
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** from each interrupt handler to the next.
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*/
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/* Gates for the standard Timer Unit (TMU) */
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.global _inth_tmu /* 128 bytes */
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/* Gates for the extra timers (informally called ETMU) */
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.global _inth_etmu2 /* 32 bytes */
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.global _inth_etmu_help /* 32 bytes */
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.global _inth_etmux /* 32 bytes */
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.section .gint.blocks, "ax"
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.align 4
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/* TMU INTERRUPT HANDLERS - 128 BYTES
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Unfortunately I did not manage to write a handler that cleared the interrupt
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flag and invoked a callback in less than 34 bytes data included. So I
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decided to make several gates operate as a whole and add a bit more features
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in them. Basically, these handlers:
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- Clear the interrupt flag
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- Invoke a callback function and pass it a user-provided argument
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- Stop the timer if the callback returns non-zero
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- Host their own callback pointers and arguments
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It is important to notice that the code of the following gates looks like
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they are contiguous in memory. The assembler will make that assumption, and
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turn any address reference between two gates into a *relative displacement*.
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If the gates don't have the same relative location at runtime, the code will
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crash because we will have broken the references. This is why we can only do
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it with handlers that are mapped to consecutive event codes. */
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_inth_tmu:
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/* FIRST GATE - TMU0 entry, clear underflow flag and call back */
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_inth_tmu_0:
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mova .storage0, r0
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mov #0, r1
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/*** This is the first shared section ***/
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.shared1:
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sts.l pr, @-r15
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mov.l r1, @-r15
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/* Load the TCR address */
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mov.l .mask, r3
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not r3, r4
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mov.l @(8, r0), r1
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/* Clear the interrupt flag */
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1: mov.w @r1, r2
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tst r4, r2
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and r3, r2
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mov.w r2, @r1
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bf 1b
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/* Prepare callback and jump to second section */
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mov.l .gint_inth_callback_1, r1
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mov.l @r0, r4
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bra .shared2
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mov.l @(4, r0), r5
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/* SECOND GATE - TMU1 entry and stop timer */
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_inth_tmu_1:
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mova .storage1, r0
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bra .shared1
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mov #1, r1
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/*** This is the second shared section ***/
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.shared2:
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/* Invoke callback */
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jsr @r1
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nop
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/* Stop the timer if the return value is not zero */
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mov.l @r15+, r4
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tst r0, r0
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bt .shared3
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mov.l .timer_stop_1, r1
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jsr @r1
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nop
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.shared3:
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lds.l @r15+, pr
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rts
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nop
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.zero 4
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/* THIRD GATE - TMU2 entry and storage for TMU0 */
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_inth_tmu_2:
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mova .storage2, r0
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bra .shared1
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mov #2, r1
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.zero 10
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.gint_inth_callback_1:
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.long _gint_inth_callback
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.storage0:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0xa4490010 /* TCR0: Overridden at startup on SH3 */
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/* FOURTH GATE - Storage for TMU1, TMU2 and other values */
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_inth_tmu_storage:
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.mask:
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.long 0xfffffeff
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.timer_stop_1:
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.long _timer_stop
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.storage1:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0xa449001c /* TCR1: Overridden at startup on SH3 */
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.storage2:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0xa4490028 /* TCR2: Overridden at startup on SH3 */
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/* EXTRA TMU INTERRUPT HANDLERS - 96 BYTES
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To implement the same functionalities as the standard timers, several blocks
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are once again needed. But the handlers for the extra timers are not located
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in adjacent gates, except for ETMU1 and ETMU2 which have event codes 0xc20
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and 0xc40. Since handler 0xc60 is free on SH4 and not redirected to on SH3,
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I use it to build a three-handler block similar to that of the TMU above.
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On SH4 this means that an extra gate has to be installed, but no interrupt
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point here. On SH3 this means that four gates are used for the only extra
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timer, but the incurred cost is minimal (96 bytes on the binary file)
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because the size of the VBR area can hardly be shrunk anyway.
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It *is* possible to do generalized communication between interrupt handlers
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that do not reside in consecutive gates. The general way of performing a
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jump or data access between two interrupt handlers would be to store at
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runtime the address of the target resource in a reserved longword in the
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source handler. But longwords are costly in 32-byte areas. Even if the event
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codes of the interrupt handlers are known at development time, the best I
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can think of is hardcoding the relative displacements, and one would need to
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use the unnatural and unmaintainable @(disp, pc) addressing modes. */
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/* FIRST GATE - ETMU2 entry, invoke callback and prepare clear flag */
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_inth_etmu2:
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mova .storage_etmu2, r0
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mov #5, r1
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.shared4:
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mov.l r1, @-r15
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sts.l pr, @-r15
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mov.l r0, @-r15
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/* Clear interrupt flag */
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mov.l .timer_clear, r2
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jsr @r2
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mov r1, r4
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/* Prepare invoking the callback function */
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mov.l @r15+, r0
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mov.l .gint_inth_callback_2, r1
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bra _inth_etmu_help
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mov.l @r0, r4
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.storage_etmu2:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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/* SECOND GATE - Helper entry, invoke callback and stop timer if requested */
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_inth_etmu_help:
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/* Invoke callback; if return value is non-zero, stop timer */
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jsr @r1
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mov.l @(4, r0), r5
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tst r0, r0
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bt .shared5
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mov.l .timer_stop_2, r1
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jsr @r1
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mov.l @(4, r15), r4
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/* Clear the flag and possibly stop the timer */
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.shared5:
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lds.l @r15+, pr
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rts
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add #4, r15
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.gint_inth_callback_2:
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.long _gint_inth_callback
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.timer_clear:
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.long _timer_clear
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.timer_stop_2:
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.long _timer_stop
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/* THIRD GATE - All other ETMU entries, deferred to the previous ones */
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_inth_etmux:
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/* Dynamically compute the target of the jump */
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stc vbr, r3
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mov.l 1f, r2
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add r2, r3
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mova .storage_etmux, r0
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mov.l .id_etmux, r1
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jmp @r3
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nop
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nop
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/* Offset from VBR where extra timer 2 is located:
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* 0x600 to reach the interrupt handlers
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* 0x040 to jump over the entry gate
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* 0x840 to reach the handler of ETMU2
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* Skip over the first instructions
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This is different on SH3 due to the compact scheme so it's edited
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dynamically at install time. */
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1: .long 0xe80 + (.shared4 - _inth_etmu2)
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.id_etmux:
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.long 0 /* Timer ID */
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.storage_etmux:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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