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https://git.planet-casio.com/Lephenixnoir/gint.git
synced 2025-01-06 08:53:36 +01:00
688 lines
16 KiB
C
688 lines
16 KiB
C
#ifndef _MODULES_INTERRUPTS
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#define _MODULES_INTERRUPTS
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#include <modules/macros.h>
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#include <stdint.h>
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//---
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// Interrupt controller.
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// This part is difficult to handle, because the interrupt controllers of
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// SH7705 and SH7305 MPUs have virtually nothing in common. I eventually
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// decided to completely split it up into two kinds of structures and
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// types.
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// Use the gint API, not this module, for platform-independent interrupt
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// management.
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//---
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//---
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// SH7705-related definitions.
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//---
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/*
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mod_intc_ipc_7705_t
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Interrupt priority controller. Just a bunch of 16-bit-registers that
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handle the interrupt priority of all interrupt sources.
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Please note that because the interrupt priority controller of the
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SH7705 MPU has registers scattered everywhere in the memory, its
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structure below has a different pointer for each register. On the
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opposite, the SH7305 registers are all in a contiguous area thus there
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is only one pointer for the whole group.
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*/
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typedef struct
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{
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volatile word_union(*IPRA,
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uint TMU0 :4; /* Timer 0 */
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uint TMU1 :4; /* Timer 1 */
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uint TMU2 :4; /* Timer 2 */
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uint RTC :4; /* Real-Time Clock */
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);
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volatile word_union(*IPRB,
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uint WDT :4; /* Watchdog Timer */
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uint REF :4; /* BSC Refresh Request, SDRAM (?) */
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uint :4;
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uint :4;
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);
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volatile word_union(*IPRC,
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uint IRQ3 :4; /* Interrupt request 3 */
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uint IRQ2 :4; /* Interrupt request 2 */
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uint IRQ1 :4; /* Interrupt request 1 */
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uint IRQ0 :4; /* Interrupt request 0 */
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);
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volatile word_union(*IPRD,
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uint PINT0_7 :4; /* External interrupt pins 0 to 7 */
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uint PINT8_15 :4; /* External interrupt pins 8 to 15 */
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uint IRQ5 :4; /* Interrupt request 5 */
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uint IRQ4 :4; /* Interrupt request 4 */
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);
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volatile word_union(*IPRE,
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uint DMAC :4; /* Direct Memory Access Controller */
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uint SCIF0 :4; /* Serial Communication Interface 0 */
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uint SCIF2 :4; /* Serial Communication Interface 2 */
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uint ADC :4; /* Analog/Decimal Converter */
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);
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volatile word_union(*IPRF,
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uint :4;
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uint :4;
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uint USB :4; /* USB Controller */
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uint :4;
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);
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volatile word_union(*IPRG,
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uint TPU0 :4; /* Timer Pulse Unit 0 */
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uint TPU1 :4; /* Timer Pulse Unit 1 */
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uint :4;
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uint :4;
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);
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volatile word_union(*IPRH,
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uint TPU2 :4; /* Timer Pulse Unit 2 */
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uint TPU3 :4; /* Timer Pulse Unit 3 */
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uint :4;
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uint :4;
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);
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} __attribute__((packed)) mod_intc_ipc_7705_t;
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/*
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mod_intc_icr0_7705_t
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Interrupt control register 0: configuration of the NMI interrupt.
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*/
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typedef struct
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{
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word_union(,
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uint const NMIL :1; /* NMI Input Level */
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uint :6;
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uint NMIE :1; /* NMI Edge Select */
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uint :8;
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);
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} __attribute__((packed, aligned(2))) mod_intc_icr0_7705_t;
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/*
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mod_intc_icr1_7705_t
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Interrupt control register 1: general interrupt configuration.
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*/
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typedef struct
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{
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word_union(,
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uint MAI :1; /* Mask All Interrupts */
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uint IRQLVL :1; /* Interrupt Request Level Detect */
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uint BLMSK :1; /* Enable NMI when BL is set */
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uint :1;
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uint IRQ5E :2; /* IRQ 5 Edge Detection */
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uint IRQ4E :2;
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uint IRQ3E :2;
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uint IRQ2E :2;
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uint IRQ1E :2;
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uint IRQ0E :2;
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);
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} __attribute__((packed, aligned(2))) mod_intc_icr1_7705_t;
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/*
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mod_intc_icr2_7705_t
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Interrupt control register 2: individual PINT interrupt management.
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*/
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typedef struct
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{
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word_union(,
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uint PINT15 :1; /* PINT15 interrupt detection level */
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uint PINT14 :1;
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uint PINT13 :1;
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uint PINT12 :1;
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uint PINT11 :1;
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uint PINT10 :1;
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uint PINT9 :1;
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uint PINT8 :1;
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uint PINT7 :1;
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uint PINT6 :1;
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uint PINT5 :1;
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uint PINT4 :1;
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uint PINT3 :1;
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uint PINT2 :1;
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uint PINT1 :1;
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uint PINT0 :1;
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);
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} __attribute__((packed, aligned(2))) mod_intc_icr2_7705_t;
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/*
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mod_intc_pinter_7705_t
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PINTER register: individual masks for all PINT interrupts.
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*/
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typedef struct
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{
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word_union(,
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uint PINT15 :1; /* PINT15 interrupt enable */
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uint PINT14 :1;
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uint PINT13 :1;
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uint PINT12 :1;
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uint PINT11 :1;
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uint PINT10 :1;
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uint PINT9 :1;
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uint PINT8 :1;
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uint PINT7 :1;
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uint PINT6 :1;
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uint PINT5 :1;
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uint PINT4 :1;
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uint PINT3 :1;
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uint PINT2 :1;
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uint PINT1 :1;
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uint PINT0 :1;
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);
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} __attribute__((packed, aligned(2))) mod_intc_pinter_7705_t;
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/*
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mod_intc_irr0_7705_t
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Interrupt Request Register 0: Indicates whether interrupt requests are
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being input to the various interrupt lines. Also allows to clear the
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IRQ request bits in edge-detection mode.
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*/
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typedef struct
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{
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byte_union(,
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uint const PINT0_7R :1; /* PINT0-7 state */
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uint const PINT8_15R :1; /* PINT8-15 state */
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uint IRQ5 :1; /* IRQ5 request pin state */
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uint IRQ4 :1;
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uint IRQ3 :1;
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uint IRQ2 :1;
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uint IRQ1 :1;
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uint IRQ0 :1;
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);
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} __attribute__((packed)) mod_intc_irr0_7705_t;
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/*
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mod_intc_irr1_7705_t
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Interrupt Request Register 1: State of SCIF0 and DMAC requests.
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*/
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typedef struct
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{
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const byte_union(,
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uint TXIOR :1; /* SCIF0 TXI interrupt */
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uint :1;
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uint RXI0R :1; /* SCIF0 RXI interrupt */
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uint ERI0R :1; /* SCIF0 ERI interrupt */
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uint DEI3R :1; /* DMAC DEI3 interrupt */
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uint DEI2R :1; /* DMAC DEI2 interrupt */
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uint DEI1R :1; /* DMAC DEI1 interrupt */
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uint DEI0R :1; /* DMAC DEI0 interrupt */
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);
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} __attribute__((packed)) mod_intc_irr1_7705_t;
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/*
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mod_intc_irr2_7705_t
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Interrupt Request Register 2: State of SCIF2 and ADC requests.
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*/
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typedef struct
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{
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const byte_union(,
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uint :3;
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uint ADIR :1; /* AD/C ADI interrupt */
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uint TXI2R :1; /* SCIF2 TXI interrupt */
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uint :1;
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uint RXI2R :1; /* SCIF2 RXI interrupt */
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uint ERI2R :1; /* SCIF2 ERI interrupt */
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);
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} __attribute__((packed, aligned(2))) mod_intc_irr2_7705_t;
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/*
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mod_intc_7705_t
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Finally the SH7705 interrupt controller.
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*/
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typedef struct
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{
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/* All interrupt priority registers */
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mod_intc_ipc_7705_t iprs;
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/* Control registers */
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volatile mod_intc_icr0_7705_t *ICR0;
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volatile mod_intc_icr1_7705_t *ICR1;
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volatile mod_intc_icr2_7705_t *ICR2;
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/* PINTER register */
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volatile mod_intc_pinter_7705_t *PINTER;
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/* Interrupt request registers */
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volatile mod_intc_irr0_7705_t *IRR0;
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volatile mod_intc_irr1_7705_t *IRR1;
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volatile mod_intc_irr2_7705_t *IRR2;
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} __attribute__((packed)) mod_intc_7705_t;
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//---
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// SH7305-related definitions.
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//---
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/*
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mod_intc_ipc_7305_t
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Interrupt priority controller, same idea as the previous one.
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Some of the interrupt fields of the SH7305 registers, the contents of
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which have been directly taken from the SH7724 documentation, have been
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left unnamed because the related peripheral modules are *very* unlikely
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to even exist in the SH7305, let alone be of any use to us.
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*/
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typedef struct
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{
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word_union(IPRA,
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uint TMU0_0 :4; /* TMU0 Channel 0 */
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uint TMU0_1 :4; /* TMU0 Channel 1 */
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uint TMU0_2 :4; /* TMU0 Channel 2 */
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uint IrDA :4; /* Infrared Communication */
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);
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pad(2);
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word_union(IPRB,
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uint :4; /* JPEG Processing Unit */
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uint LCDC :4; /* LCD Controller */
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uint DMAC1A :4; /* Direct Memory Access Controller 1 */
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uint :4; /* Blending Engine Unit */
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);
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pad(2);
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word_union(IPRC,
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uint TMU1_0 :4; /* TMU1 Channel 0 */
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uint TMU1_1 :4; /* TMU1 Channel 1 */
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uint TMU1_2 :4; /* TMU1 Channel 2 */
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uint :4; /* Sound Processing Unit */
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);
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pad(2);
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word_union(IPRD,
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uint :4;
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uint MMCIF :4; /* MultiMedia Card Interface */
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uint :4;
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uint :4; /* ATAPI Interface */
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);
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pad(2);
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word_union(IPRE,
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uint DMAC0A :4; /* Direct Memory Access Controller 0 */
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uint :4; /* Various graphical engines */
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uint SCIFA3 :4; /* SCIFA channel 3 interrupt */
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uint :4; /* Video Processing Unit */
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);
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pad(2);
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word_union(IPRF,
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uint KEYSC :4; /* Key Scan Interface */
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uint DMACOB :4; /* DMAC0 transfer/error info */
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uint USB0_1 :4; /* USB controller */
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uint CMT :4; /* Compare Match Timer */
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);
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pad(2);
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word_union(IPRG,
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uint SCIF0 :4; /* SCIF0 transfer/error info */
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uint SCIF1 :4; /* SCIF1 transfer/error info */
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uint SCIF2 :4; /* SCIF2 transfer/error info */
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uint :4; /* Video Engine Unit */
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);
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pad(2);
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word_union(IPRH,
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uint MSIOF0 :4; /* Clock-synchronized SCIF channel 0 */
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uint MSIOF1 :4; /* Clock-synchronized SCIF channel 1 */
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uint :4; /* I2C Interface channel 0 */
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uint :4; /* I2C Interface channel 1 */
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);
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pad(2);
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word_union(IPRI,
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uint SCIFA4 :4; /* SCIFA channel 4 interrupt */
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uint :4; /* MediaRAM InterConnected Buffers */
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uint :4; /* Transport Stream Interface */
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uint :4; /* 2D Graphics Accelerator & ICB */
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);
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pad(2);
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word_union(IPRJ,
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uint :4; /* Capture Engine Unit */
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uint :4; /* Ethernet Memory Access Controller */
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uint FSI :4; /* FIFO-Buffered Serial Interface */
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uint SDHI1 :4; /* SD Card Host Interface channel 1 */
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);
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pad(2);
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word_union(IPRK,
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uint RTC :4; /* Real-Time Clock */
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uint DMAC1B :4; /* DMAC1 transfer/error info */
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uint :4; /* MediaRAM InterConnected Buffers */
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uint SDHI0 :4; /* SD Card Host Interface channel 0 */
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);
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pad(2);
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word_union(IPRL,
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uint SCIFA5 :4; /* SCIFA channel 5 interrupt */
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uint :4;
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uint TPU :4; /* Timer-Pulse Unit */
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uint :4; /* Image Extraction DMAC */
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);
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pad(2);
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} __attribute((packed, aligned(4))) mod_intc_ipc_7305_t;
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/*
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mod_intc_icr0_7305_t
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Interrupt Control Register 0: Detection mode of external pins.
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*/
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typedef struct
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{
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word_union(,
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uint const NMIL :1; /* NMI Input Level */
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uint MAI :1; /* Mask All Interrupts */
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uint :4;
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uint NMIB :1; /* Enable NMI when BL is set */
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uint NMIE :1; /* NMI Edge Selection */
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uint :2;
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uint LVLMODE :1; /* Level-Sensed IRQ Retention Mode */
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uint :5;
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);
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} __attribute__((packed, aligned(2))) mod_intc_icr0_7305_t;
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/*
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mod_intc_icr1_7305_t
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Interrupt Control Register 1: Manages detection of IRQ interrupts
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*/
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typedef struct
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{
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word_union(,
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uint IRQ0 :2; /* IRQ0 Sense (Edge) Select */
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uint IRQ1 :2;
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uint IRQ2 :2;
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uint IRQ3 :2;
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uint IRQ4 :2;
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uint IRQ5 :2;
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uint IRQ6 :2;
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uint IRQ7 :2;
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);
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} __attribute__((packed, aligned(2))) mod_intc_icr1_7305_t;
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/*
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mod_intc_intpri00_7305_t
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Interrupt Priority 00: Priority settings for IRQ interrupts.
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*/
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typedef struct
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{
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lword_union(,
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uint IRQ0 :4; /* IRQ0 Interrupt Priority */
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uint IRQ1 :4;
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uint IRQ2 :4;
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uint IRQ3 :4;
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uint IRQ4 :4;
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uint IRQ5 :4;
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uint IRQ6 :4;
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uint IRQ7 :4;
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);
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} __attribute((packed, aligned(4))) mod_intc_intpri00_7305_t;
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/*
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mod_intc_intreq00_7305_t
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Interrupt Request 00: Request information of IRQ interrupts. Each of
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these bits indicates whether an interrupt is being input.
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mod_intc_intmsk00_7305_t
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Interrupt Mask 00: Set interrupt mask for IRQ interrupts. Writing 0 to
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these bits is ignored, writing 1 masks the interrupt.
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mod_intc_intmskclr00_7305_t
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Interrupt Mask Clear 00: Clear interrupt mask for IRQ interrupts.
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Writing 0 to these bits is ignored, writing 1 clears the mask.
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*/
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typedef struct
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{
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byte_union(,
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uint IRQ0 :1;
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uint IRQ1 :1;
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uint IRQ2 :1;
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uint IRQ3 :1;
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uint IRQ4 :1;
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uint IRQ5 :1;
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uint IRQ6 :1;
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uint IRQ7 :1;
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);
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} __attribute__((packed)) mod_intc_irq_7305_t;
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typedef mod_intc_irq_7305_t mod_intc_intreq00_7305_t;
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typedef mod_intc_irq_7305_t mod_intc_intmsk00_7305_t;
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typedef mod_intc_irq_7305_t mod_intc_intmskclr00_7305_t;
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/*
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mod_intc_masks_7305_t
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A set of bits to mask individual interrupts.
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- Masking interrupts is realized by writing 1 to IMRs ;
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- Clearing masks is realized by writing 1 to IMCRs ;
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Using the wrong register set, such as writing 0 to IMRs to clear a
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mask, will be ignored and have no effect. Reading from IMCRs yields an
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undefined value.
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*/
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typedef struct
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{
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byte_union(IMR0,
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uint :1;
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uint TUNI1_2 :1; /* TMU1 overflow interrupts */
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uint TUNI1_1 :1;
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uint TUNI1_0 :1;
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uint SDHII3 :1; /* SD Card Host 1 interrupts */
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uint SDHII2 :1;
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uint SDHII1 :1;
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uint SDHII0 :1;
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);
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pad(3);
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byte_union(IMR1,
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uint :4;
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uint DEI3 :1; /* DMAC0A interrupts */
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uint DEI2 :1;
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uint DEI1 :1;
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uint DEI0 :1;
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);
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pad(3);
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byte_union(IMR2,
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uint :7;
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uint SCIFA0 :1; /* Asynchronous Serial interrupts */
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);
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pad(3);
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byte_union(IMR3,
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uint DEI3 :1; /* DMAC1A interrupts */
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uint DEI2 :1;
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uint DEI1 :1;
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uint DEI0 :1;
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uint :4;
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);
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pad(3);
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byte_union(IMR4,
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uint :1;
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uint TUNI0_2 :1; /* TMU0 overflow interrupts */
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uint TUNI0_1 :1;
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uint TUNI0_0 :1;
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uint :3;
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uint LCDCI :1; /* LCD Controller Interrupt */
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);
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pad(3);
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byte_union(IMR5,
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uint KEYI :1; /* Key Interface */
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uint DADERR :1; /* DMAC0B interrupts */
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uint DEI5 :1;
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uint DEI4 :1;
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uint :1;
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uint SCIF2 :1; /* Serial Communication Interface */
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uint SCIF1 :1;
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uint SCIF0 :1;
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|
);
|
|
pad(3);
|
|
|
|
byte_union(IMR6,
|
|
uint :2;
|
|
uint :1;
|
|
uint SCIFA4 :1; /* SCIFA4 interrupt */
|
|
uint :1;
|
|
uint :1;
|
|
uint MSIOFI0 :1; /* Clock-synchronized SCIF channel 0 */
|
|
uint MSIOFI1 :1; /* Clock-synchronized SCIF channel 1 */
|
|
);
|
|
pad(3);
|
|
|
|
uint8_t IMR7;
|
|
pad(3);
|
|
|
|
byte_union(IMR8,
|
|
uint SDHII3 :1; /* SD Card Host 0 interrupts */
|
|
uint SDHII2 :1;
|
|
uint SDHII1 :1;
|
|
uint SDHII0 :1;
|
|
uint :2;
|
|
uint SCFIA5 :1; /* SCIFA5 interrupt */
|
|
uint FSI :1; /* FIFO-Buffered Serial Interface */
|
|
);
|
|
pad(3);
|
|
|
|
byte_union(IMR9,
|
|
uint :3;
|
|
uint CMTI :1; /* Compare Match Timer Interrupt */
|
|
uint :1;
|
|
uint USI1 :1; /* USB1 */
|
|
uint USI0 :1; /* USB0 */
|
|
uint :1;
|
|
);
|
|
pad(3);
|
|
|
|
byte_union(IMR10,
|
|
uint :1;
|
|
uint DADERR :1; /* DMAC1B interrupts */
|
|
uint DEI5 :1;
|
|
uint DEI4 :1;
|
|
uint :1;
|
|
uint ATI :1; /* RTC Alarm interrupt */
|
|
uint PRI :1; /* RTC Periodic interrupt */
|
|
uint CUI :1; /* RTC Carry interrupt */
|
|
);
|
|
pad(3);
|
|
|
|
byte_union(IMR11,
|
|
uint :5;
|
|
uint TPUI :1; /* Timer-Pulse Unit */
|
|
uint :2;
|
|
);
|
|
pad(3);
|
|
|
|
uint8_t IMR12;
|
|
char gap2[15];
|
|
|
|
} __attribute__((packed, aligned(4))) mod_intc_masks_7305_t;
|
|
|
|
/*
|
|
mod_intc_userimask_7305_t
|
|
User Interrupt Mask: Specifies the minimum required level for
|
|
interrupts to be accepted.
|
|
|
|
WARNING: Writing to this register requires the eight upper bits of the
|
|
operand (ie. the new value of USERIMASK) to be 0xa5; otherwise, the
|
|
write is ignored. To modify the value of this register, do not access
|
|
the bit field directly, backup the variable and modify it:
|
|
|
|
void set_user_imask(int new_level)
|
|
{
|
|
mod_intc_userimask_7305_t mask = *(INTC._7305.USERIMASK);
|
|
mask._0xa5 = 0xa5;
|
|
mask.UIMASK = new_level & 0x0f;
|
|
*(INTC._7305.USERIMASK) = mask;
|
|
}
|
|
*/
|
|
typedef struct
|
|
{
|
|
lword_union(,
|
|
uint _0xa5 :8; /* Always set to 0xa5 before writing */
|
|
uint :16;
|
|
uint UIMASK :4; /* User Interrupt Mask Level */
|
|
uint :4;
|
|
);
|
|
|
|
} __attribute__((packed, aligned(4))) mod_intc_userimask_7305_t;
|
|
|
|
/*
|
|
mod_intc_nmifcr_7305_t
|
|
NMI Flag Control Register: Indicates the state of the NMI pin and the
|
|
NMI interrupt request.
|
|
*/
|
|
typedef struct
|
|
{
|
|
word_union(,
|
|
uint const NMIL :1; /* NMI Interupt Level */
|
|
uint :14;
|
|
uint NMIFL :1; /* NMI Interrupt Request Flag */
|
|
);
|
|
|
|
} __attribute__((packed, aligned(2))) mod_intc_nmifcr_7305_t;
|
|
|
|
/*
|
|
mod_intc_7305_t
|
|
Finally the whole interrupt controller.
|
|
*/
|
|
typedef struct
|
|
{
|
|
/* Control registers */
|
|
volatile mod_intc_icr0_7305_t *ICR0;
|
|
volatile mod_intc_icr1_7305_t *ICR1;
|
|
|
|
/* Interrupt priority registers */
|
|
volatile mod_intc_intpri00_7305_t *INTPRI00;
|
|
volatile mod_intc_ipc_7305_t *iprs;
|
|
|
|
/* Interrupt mask & mask clear registers */
|
|
volatile mod_intc_intmsk00_7305_t *INTMSK00;
|
|
volatile mod_intc_masks_7305_t *masks;
|
|
volatile mod_intc_intmskclr00_7305_t *INTMSKCLR00;
|
|
volatile mod_intc_masks_7305_t *masks_clear;
|
|
|
|
/* Other registers */
|
|
volatile mod_intc_intreq00_7305_t *INTREQ00;
|
|
volatile mod_intc_userimask_7305_t *USERIMASK;
|
|
volatile mod_intc_nmifcr_7305_t *NMIFCR;
|
|
|
|
} mod_intc_7305_t;
|
|
|
|
|
|
|
|
//---
|
|
// Platform-independent structures.
|
|
// Unfortunately there is nothing here. Users willing to manage interrupts
|
|
// using the INTC register will have to handle explicitely both platforms.
|
|
//---
|
|
|
|
/*
|
|
mod_intc_t
|
|
Interrupt Controller.
|
|
*/
|
|
typedef union
|
|
{
|
|
mod_intc_7705_t _7705;
|
|
mod_intc_7305_t _7305;
|
|
|
|
} __attribute__((packed)) mod_intc_t;
|
|
|
|
// Here's what you'll need to use.
|
|
extern mod_intc_t INTC;
|
|
|
|
#endif // _MODULE_INTERRUPTS
|