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9cf2f9fe97
This change includes three reliability improvements in handlers: 1. TMU handlers now actively check for the UNF flag to go low rather than expecting it to do so right away. 2. CPUOPM.INTMU is now set so that IMASK it updated at every interrupt (which is absolutely required for nested interrupts!). 3. gint_inth_callback() no longer performs transfers between user bank and kernel bank while in user bank, because this is when interrupts are enabled and thus likely to corrupt the kernel bank; rather, it now does it while in kernel bank with interrupts disabled.
36 lines
1 KiB
C
36 lines
1 KiB
C
//---
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// core:setup - Installing and unloading the library
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//---
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#ifndef GINT_CORE_SETUP
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#define GINT_CORE_SETUP
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#include <gint/defs/types.h>
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/* Prototypes for the library management functions are in <gint/gint.h> */
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/* gint_setvbr()
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Changes the VBR address and calls the configuration function while
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interrupts are disabled. The configuration function must disable all
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interrupts that the new handlers cannot handle, either by clearing the
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priority registers or by setting the interrupt masks.
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@vbr New VBR address
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@configure Configuration function
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Returns the previous VBR address. */
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uint32_t gint_setvbr(uint32_t vbr, void (*configure)(void));
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void gint_setcpuopm(uint32_t CPUOPM);
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uint32_t gint_getcpuopm(void);
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/* gint_exch(): Exception handler */
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void gint_exch(void);
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/* gint_tlbh(): TLB miss handler */
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void gint_tlbh(void);
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/* gint_inth_7705(): SH7705 exception handler */
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void gint_inth_7705(void);
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/* gint_inth_7305(): SH7305 exception handler */
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void gint_inth_7305(void);
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#endif /* GINT_CORE_SETUP */
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