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e5abe03b89
This commit introduces a large architectural change. Unlike previous
models of the fx-9860G series, the G-III models have a new user RAM
address different from 8801c000. The purpose of this change is to
dynamically load GMAPPED functions to this address by querying the TLB,
and call them through a function pointer whose address is determined
when loading.
Because of the overhead of using a function pointer in both assembly and
C code, changes have been made to avoid GMAPPED functions altogether.
Current, only cpu_setVBR() and gint_inth_callback() are left, the second
being used specifically to enable TLB misses when needed.
* Add a .gint.mappedrel section for the function pointers holding
addresses to GMAPPED functions; add function pointers for
cpu_setVBR() and gint_inth_callback()
* Move rram to address 0 instead of the hardcoded 0x8801c000
* Load GMAPPED functions at their linked address + the physical address
user RAM is mapped, to and compute their function pointers
* Remove the GMAPPED macro since no user function needs it anymore
* Add section flags "ax" (code) or "aw" (data) to every custom .section
in assembler code, as they default to unpredictable values that can
cause the section to be marked NOLOAD by the linker
* Update the main kernel, TMU, ETMU and RTC interrupt handlers to use
the new indirect calling method
This is made possible by new MMU functions giving direct access to the
physical area behind any virtualized page.
* Add an mmu_translate() function to query the TLB
* Add an mmu_uram() function to access user RAM from P1
The exception catching mechanism has been modified to avoid the use of
GMAPPED functions altogether.
* Set SR.BL=0 and SR.IMASK=15 before calling exception catchers
* Move gint_exc_skip() to normal text ROM
* Also fix registers not being popped off the stack before a panic
The timer drivers have also been modified to avoid GMAPPED functions.
* Invoke timer_stop() through gint_inth_callback() and move it to ROM
* Move and expand the ETMU driver to span 3 blocks at 0xd00 (ETMU4)
* Remove the timer_clear() function by inlining it into the ETMU handler
(TCR is provided within the storage block of each timer)
* Also split src/timer/inth.s into src/timer/inth-{tmu,etmu}.s
Additionally, VBR addresses are now determined at runtime to further
reduce hardcoded memory layout addresses in the linker script.
* Determine fx-9860G VBR addresses dynamically from mmu_uram()
* Determine fx-CG 50 VBR addresses dynamically from mmu_uram()
* Remove linker symbols for VBR addresses
Comments and documentation have been updated throughout the code to
reflect the changes.
121 lines
3 KiB
ArmAsm
121 lines
3 KiB
ArmAsm
/*
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** gint:tmu:inth-tmu - Interrupt handlers for the timer units
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** Perhaps the most technical of my interrupt handlers. They implement a
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** simple kind of interrupt handler communication by letting the control flow
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** from each interrupt handler to the next.
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*/
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/* Gates for the standard Timer Unit (TMU) */
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.global _inth_tmu /* 128 bytes */
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.section .gint.blocks, "ax"
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.align 4
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/* TMU INTERRUPT HANDLERS - 128 BYTES
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Unfortunately I did not manage to write a handler that cleared the interrupt
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flag and invoked a callback in less than 34 bytes data included. So I
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decided to make several gates operate as a whole and add a bit more features
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in them. Basically, these handlers:
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- Clear the interrupt flag
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- Invoke a callback function and pass it a user-provided argument
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- Stop the timer if the callback returns non-zero
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- Host their own callback pointers and arguments
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It is important to notice that the code of the following gates looks like
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they are contiguous in memory. The assembler will make that assumption, and
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turn any address reference between two gates into a *relative displacement*.
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If the gates don't have the same relative location at runtime, the code will
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crash because we will have broken the references. This is why we can only do
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it with handlers that are mapped to consecutive event codes. */
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_inth_tmu:
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/* FIRST GATE - TMU0 entry, clear underflow flag and call back */
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_inth_tmu_0:
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mova .storage0, r0
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mov #0, r1
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/*** This is the first shared section ***/
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.shared1:
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mov.l r8, @-r15
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sts.l pr, @-r15
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mov.l r1, @-r15
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/* Load the TCR address */
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mov.l .mask, r3
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not r3, r4
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mov.l @(8, r0), r1
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/* Clear the interrupt flag */
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1: mov.w @r1, r2
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tst r4, r2
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and r3, r2
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mov.w r2, @r1
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bf 1b
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/* Prepare callback and jump to second section */
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mov.l .gint_inth_callback, r8
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bra .shared2
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mov.l @r8, r8
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/* SECOND GATE - TMU1 entry and stop timer */
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_inth_tmu_1:
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mova .storage1, r0
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bra .shared1
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mov #1, r1
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/*** This is the second shared section ***/
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.shared2:
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/* Invoke callback */
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mov.l @r0, r4
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jsr @r8
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mov.l @(4, r0), r5
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/* Stop the timer if the return value is not zero */
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mov.l @r15+, r5
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tst r0, r0
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bt 2f
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mov.l .timer_stop, r4
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jsr @r8
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nop
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2:
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lds.l @r15+, pr
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rts
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mov.l @r15+, r8
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.zero 2
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/* THIRD GATE - TMU2 entry and storage for TMU0 */
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_inth_tmu_2:
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mova .storage2, r0
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bra .shared1
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mov #2, r1
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.zero 10
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.gint_inth_callback:
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.long _gint_inth_callback
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.storage0:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0xa4490010 /* TCR0: Overridden at startup on SH3 */
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/* FOURTH GATE - Storage for TMU1, TMU2 and other values */
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_inth_tmu_storage:
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.mask:
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.long 0xfffffeff
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.timer_stop:
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.long _timer_stop
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.storage1:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0xa449001c /* TCR1: Overridden at startup on SH3 */
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.storage2:
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.long 0 /* Callback: Configured dynamically */
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.long 0 /* Argument: Configured dynamically */
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.long 0xa4490028 /* TCR2: Overridden at startup on SH3 */
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