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https://git.planet-casio.com/Lephenixnoir/gint.git
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92 lines
1.3 KiB
ArmAsm
92 lines
1.3 KiB
ArmAsm
/*
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** gint:core:vbr - Assembler-level VBR management
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*/
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.global _cpu_setVBR
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.global _cpu_setCPUOPM
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.global _cpu_getCPUOPM
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.global _cpu_getSR
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.global _cpu_setSR
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/* cpu_setVBR(): Change VBR address */
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.section .gint.mapped, "ax"
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_cpu_setVBR_reloc:
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mov.l r8, @-r15
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mov.l r9, @-r15
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sts.l pr, @-r15
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/* Block all interrupts by setting IMASK=15 */
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mov #0xf, r9
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shll2 r9
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shll2 r9
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stc sr, r0
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or r9, r0
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ldc r0, sr
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/* Set the new VBR address */
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stc vbr, r8
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ldc r4, vbr
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/* Call the configuration function */
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jsr @r5
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mov r6, r4
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/* Enable interrupts again */
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stc sr, r0
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not r9, r9
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and r9, r0
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ldc r0, sr
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/* Return the previous VBR address */
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mov r8, r0
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lds.l @r15+, pr
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mov.l @r15+, r9
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rts
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mov.l @r15+, r8
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.section .gint.mappedrel, "aw"
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_cpu_setVBR:
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.long _cpu_setVBR_reloc
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.text
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/* cpu_setCPUOPM(): Change the CPU Operation Mode register */
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_cpu_setCPUOPM:
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/* Set CPUOPM as requested */
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mov.l 1f, r0
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mov.l r4, @r0
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/* Read CPUOPM again */
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mov.l @r0, r5
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/* Invalidate a cache address */
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mov #-96, r0
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shll16 r0
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shll8 r0
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icbi @r0
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rts
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nop
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/* cpu_getCPUOPM(): Get the CPU OperatioN Mode register */
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_cpu_getCPUOPM:
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mov.l 1f, r0
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rts
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mov.l @r0, r0
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.align 4
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1: .long 0xff2f0000
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/* cpu_getSR(): Get status register */
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_cpu_getSR:
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stc sr, r0
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rts
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nop
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/* cpu_setSR(): Set status register */
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_cpu_setSR:
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ldc r4, sr
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rts
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nop
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