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https://git.planet-casio.com/Lephenixnoir/gint.git
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d8886c7dbf
This change adds a TLB miss handler that calls __TLB_LoadPTEH() and removes the startu mapping of add-in pages in the explore() routine of src/core/start.c. Note that calling __TLB_LoadPTEH() manually might unexpectedly lead to a TLB multihit problem as the requested page might be accidentally loaded by a TLB miss in the code that loads it. A TLB multihit is a platform reset, so this function should always be considered unsafe to call (unless the calling code is in a combination of P1 space and ILRAM). This change also moves a lot of functions out of the .pretext section, notably topti, as this was designed to allow panic messages when the add-in couldn't be mapped entirely. By contrast, a GMAPPED macro has been defined to mark crucial kernel code and data that must remain mapped at all times. This currently puts the data in ILRAM because static RAM is not executable. An alternative will have to be found for SH3-based fx9860g machines. This version still does not allow TLB misses in timer callbacks and breaks return-to-menu in a severe way! It is not suitable for any stable application!
80 lines
1.3 KiB
C
80 lines
1.3 KiB
C
//---
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// gint:mpu:mmu - Memory Management Unit
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//
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// The MMU mainly exposes the contents of the TLB for us to inspect.
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// Functions to manipulate these are exposed by <gint/mmu.h>.
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//---
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#ifndef GINT_MPU_MMU
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#define GINT_MPU_MMU
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#include <gint/defs/attributes.h>
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#include <gint/defs/types.h>
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//---
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// SH7705 TLB. Refer to:
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// "Renesas SH7705 Group Hardware Manual"
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// Section 3: "Memory Management Unit (MMU)"
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//---
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/* tlb_addr_t - address part of a TLB entry */
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typedef struct
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{
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uint VPN :22;
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uint :1;
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uint V :1;
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uint ASID :8;
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} GPACKED(4) tlb_addr_t;
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/* tlb_data_t - data part of a TLB entry */
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typedef struct
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{
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uint :3;
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uint PPN :19;
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uint :1;
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uint V :1;
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uint :1;
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uint PR :2;
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uint SZ :1;
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uint C :1;
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uint D :1;
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uint SH :1;
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uint :1;
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} GPACKED(4) tlb_data_t;
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//---
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// SH7305 TLB. Refer to:
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// "Renesas SH7724 User's Manual: Hardware"
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// Section 7: "Memory Management Unit (MMU)"
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//---
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/* utlb_addr_t - address part of a UTLB entry */
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typedef struct
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{
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uint VPN :22;
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uint D :1;
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uint V :1;
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uint ASID :8;
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} GPACKED(4) utlb_addr_t;
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/* utlb_data_t - data part of a UTLB entry */
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typedef struct
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{
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uint :3;
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uint PPN :19;
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uint :1;
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uint V :1;
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uint SZ1 :1;
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uint PR :2;
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uint SZ2 :1;
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uint C :1;
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uint D :1;
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uint SH :1;
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uint WT :1;
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} GPACKED(4) utlb_data_t;
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#endif /* GINT_MPU_MMU */
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