mirror of
https://git.planet-casio.com/Lephenixnoir/gint.git
synced 2024-12-29 13:03:36 +01:00
c9264a06d5
Changes in the driver and world system: * Rewrite driver logic to include more advanced concepts. The notion of binding a driver to a device is introduced to formalize wait(); power management is now built-in instead of being handled by the drivers (for instance DMA). The new driver model is described in great detail in <gint/drivers.h> * Formalized the concept of "world switch" where the hardware state is saved and later restored. As a tool, the world switch turns out to be very stable, and allows a lot of hardware manipulation that would be edgy at best when running in the OS world. * Added a GINT_DRV_SHARED flag for drivers to specify that their state is shared between worlds and not saved/restored. This has a couple of uses. * Exposed a lot more of the internal driver/world system as their is no particular downside to it. This includes stuff in <gint/drivers.h> and the driver's state structures in <gint/drivers/states.h>. This is useful for debugging and for cracked concepts, but there is no API stability guarantee. * Added a more flexible driver level system that allows any 2-digit level to be used. Feature changes: * Added a CPU driver that provides the VBR change as its state save. Because the whole context switch relied on interrupts being disabled anyway, there is no longer an inversion of control when setting the VBR; this is just part of the CPU driver's configuration. The CPU driver may also support other features such as XYRAM block transfer in the future. * Moved gint_inthandler() to the INTC driver under the name intc_handler(), pairing up again with intc_priority(). * Added a reentrant atomic lock based on the test-and-set primitive. Interrupts are disabled with IMASK=15 for the duration of atomic operations. * Enabled the DMA driver on SH7305-based fx-9860G. The DMA provides little benefit on this platform because the RAM is generally faster and buffers are ultimately small. The DMA is still not available on SH3-based fx-9860G models. * Solved an extremely obnoxious bug in timer_spin_wait() where the timer is not freed, causing the callback to be called when interrupts are re-enabled. This increments a random value on the stack. As a consequence of the change, removed the long delays in the USB driver since they are not actually needed. Minor changes: * Deprecated some of the elements in <gint/hardware.h>. There really is no good way to "enumerate" devices yet. * Deprecated gint_switch() in favor of a new function gint_world_switch() which uses the GINT_CALL abstraction. * Made the fx-9860G VRAM 32-aligned so that it can be used for tests with the DMA. Some features of the driver and world systems have not been implemented yet, but may be in the future: * Some driver flags should be per-world in order to create multiple gint worlds. This would be useful in Yatis' hypervisor. * A GINT_DRV_LAZY flag would be useful for drivers that don't want to be started up automatically during a world switch. This is relevant for drivers that have a slow start/stop sequence. However, this is tricky to do correctly as it requires dynamic start/stop and also tracking which world the current hardware state belongs to.
203 lines
4.5 KiB
Text
203 lines
4.5 KiB
Text
/*
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Linker script for fxcg50 add-ins. Most symbols are used in the startup
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routine in core/start.c; some others in core/setup.c.
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*/
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/* All fxcg50 have SH4 processors (finally rid of compatibility issues) */
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OUTPUT_ARCH(sh4)
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/* ELF offers a lot of symbol/section/relocation insights */
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OUTPUT_FORMAT(elf32-sh)
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/* Located in core/start.c */
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ENTRY(_start)
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MEMORY
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{
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/* Userspace mapping of the add-in (without G3A header) */
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rom (rx): o = 0x00300000, l = 2M
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/* Static RAM; stack grows down from the end of this region.
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The first 5k (0x1400 bytes) are reserved by gint for the VBR space,
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which is loaded dynamically and accessed through P1 */
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ram (rw): o = 0x08101400, l = 507k
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/* On-chip IL memory */
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ilram (rwx): o = 0xe5200000, l = 4k
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/* On-chip X and Y memory */
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xram (rwx): o = 0xe5007000, l = 8k
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yram (rwx): o = 0xe5017000, l = 8k
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}
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SECTIONS
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{
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/*
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** ROM sections
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*/
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/* First address to be mapped to ROM */
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_brom = 0x00300000;
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/* Size of ROM mappings */
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_srom = SIZEOF(.text) + SIZEOF(.rodata)
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+ SIZEOF(.gint.drivers) + SIZEOF(.gint.blocks);
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/* Machine code going to ROM:
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- Entry function (.text.entry)
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- Compiler-provided constructors (.ctors) and destructors (.dtors)
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- All text from .text and .text.* (including user code) */
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.text : {
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*(.text.entry)
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_bctors = . ;
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*(.ctors .ctors.*)
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_ectors = . ;
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_bdtors = . ;
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*(.dtors .dtors.*)
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_edtors = . ;
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_gint_exch_start = . ;
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*(.gint.exch)
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_gint_exch_size = ABSOLUTE(. - _gint_exch_start);
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_gint_tlbh_start = . ;
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*(.gint.tlbh)
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_gint_tlbh_size = ABSOLUTE(. - _gint_tlbh_start);
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*(.text .text.*)
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} > rom
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/* gint's interrupt handler blocks (.gint.blocks)
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Although gint's blocks end up in VBR space, they are relocated at
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startup by the library/drivers, so we store them here for now */
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.gint.blocks : {
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KEEP(*(.gint.blocks));
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} > rom
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/* Exposed driver interfaces (.gint.drivers)
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The driver information is required to start and configure the
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driver, even if the symbols are not referenced */
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.gint.drivers : {
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_gint_drivers = . ;
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KEEP(*(SORT_BY_NAME(.gint.drivers.*)));
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_gint_drivers_end = . ;
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} > rom
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/* Read-only data going to ROM:
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- Resources or assets from fxconv or similar converters
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- Data marked read-only by the compiler (.rodata and .rodata.*) */
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.rodata : SUBALIGN(4) {
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/* Put these first, they need to be 4-aligned */
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*(.rodata.4)
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*(.rodata .rodata.*)
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} > rom
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/*
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** RAM sections
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*/
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. = ORIGIN(ram);
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/* BSS data going to RAM. The BSS section is to be stripped from the
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ELF file later, and wiped at startup */
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.bss (NOLOAD) : {
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_rbss = . ;
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*(.bss.vram)
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*(.bss COMMON)
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. = ALIGN(16);
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} > ram :NONE
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_sbss = SIZEOF(.bss);
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/* Read-write data sections going to RAM (.data and .data.*) */
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.data ALIGN(4) : ALIGN(4) {
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_ldata = LOADADDR(.data);
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_rdata = . ;
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*(.data .data.*)
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/* References to mapped code - no relocation needed */
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*(.gint.mappedrel)
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. = ALIGN(16);
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} > ram AT> rom
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/* Read-write data sub-aligned to 4 bytes (mainly from fxconv) */
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.data.4 : SUBALIGN(4) {
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*(.data.4)
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. = ALIGN(16);
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} > ram AT> rom
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_sdata = SIZEOF(.data) + SIZEOF(.data.4);
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/* On-chip memory sections: IL, X and Y memory */
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. = ORIGIN(ilram);
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.ilram ALIGN(4) : ALIGN(4) {
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_lilram = LOADADDR(.ilram);
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_rilram = . ;
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*(.ilram)
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/* Code that must remain mapped is placed here */
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*(.gint.mapped)
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. = ALIGN(16);
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} > ilram AT> rom
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. = ORIGIN(xram);
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.xram ALIGN(4) : ALIGN(4) {
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_lxram = LOADADDR(.xram);
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_rxram = . ;
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*(.xram)
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. = ALIGN(16);
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} > xram AT> rom
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. = ORIGIN(yram);
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.yram ALIGN(4) : ALIGN(4) {
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_lyram = LOADADDR(.yram);
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_ryram = . ;
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*(.yram)
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. = ALIGN(16);
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} > yram AT> rom
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_silram = SIZEOF(.ilram);
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_sxram = SIZEOF(.xram);
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_syram = SIZEOF(.yram);
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/* gint's uninitialized BSS section, going to static RAM. All the large
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data arrays will be located here */
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.gint.bss (NOLOAD) : {
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*(.gint.bss)
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. = ALIGN(16);
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/* End of user RAM */
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_euram = . ;
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} > ram :NONE
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_sgbss = SIZEOF(.gint.bss);
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/*
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** Unused sections
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*/
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/DISCARD/ : {
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/* SH3-only data sections */
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*(.gint.data.sh3 .gint.bss.sh3)
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/* Debug sections (often from libgcc) */
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*(.debug_info .debug_abbrev .debug_loc .debug_aranges
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.debug_ranges .debug_line .debug_str)
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/* Java class registration (why are they even here?!) */
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*(.jcr)
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/* Asynchronous unwind tables: no C++ exception handling */
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*(.eh_frame_hdr)
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*(.eh_frame)
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/* Comments or anything the compiler might generate */
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*(.comment)
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}
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}
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