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Update spec.txt

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Fcalva 2024-09-07 18:18:06 +02:00
parent 5a5bed307d
commit db7d68b317
1 changed files with 328 additions and 332 deletions
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spec.txt
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@ -2,10 +2,6 @@ instruction format:
big endian big endian
16bits 16bits
Bit order:
0 : Largest (leftmost), 7 : smallest (rightmost)
registers: registers:
r0-r12 (mov 0x0-0xc): r0-r12 (mov 0x0-0xc):
general purpose general purpose