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Fcalva 2024-09-07 18:18:06 +02:00
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instruction format: instruction format:
big endian big endian
16bits 16bits
Bit order: registers:
0 : Largest (leftmost), 7 : smallest (rightmost) r0-r12 (mov 0x0-0xc):
general purpose
8 bits
registers: r13-r15 (mov 0xd-0xf):
r0-r12 (mov 0x0-0xc): Interrupt reserved
general purpose 8 bits
8 bits ac,pr (special 0x0,1):
r13-r15 (mov 0xd-0xf): accumulator, progam counter
Interrupt reserved 16bits
8 bits ac0-1,pc0-1 (lds/sts 0x0-1,0x2-3):
ac,pr (special 0x0,1): accumulator, progam counter
accumulator, progam counter 8-8bits (lower-upper)
16bits id (special 0x2):
ac0-1,pc0-1 (lds/sts 0x0-1,0x2-3): interrupt data,
accumulator, progam counter set by the interrupt
8-8bits (lower-upper) if raised by bus
id (special 0x2): 8bits
interrupt data, in (Special 0x3):
set by the interrupt interrupt register,
if raised by bus contains the type of
8bits interrupt
in (Special 0x3): 4bits - bits 0-3 will always be 0
interrupt register, t bit:
contains the type of is set by comp ops
interrupt 1bit
4bits - bits 0-3 will always be 0 calling conventions:
t bit: r0-r1 : return registers
is set by comp ops r2-r11: call args
1bit r12 : stack pos
calling conventions: r13-15:interrupt reserved (only adressable in interrupt mode)
r0-r1 : return registers caller pushes desired return addr
r2-r11: call args to stack, callee jumps to it
r12 : stack pos
r13-15:interrupt reserved (only adressable in interrupt mode) Interrupts:
caller pushes desired return addr Hardware interrupts:
to stack, callee jumps to it 0x0 : Invalid instruction
The 15 other interrupts are free to
Interrupts: define by the user
Hardware interrupts: On interrupt (either called through
0x0 : Invalid instruction the bus or itp)
The 15 other interrupts are free to startup:
define by the user the cpu will look
On interrupt (either called through at adress 0x0,and
the bus or itp) expects to find :
startup: -0x0-1: adress of
the cpu will look the starting
at adress 0x0,and point,will be
expects to find : jumped to
-0x0-1: adress of -0x2-3: adress of
the starting the stack, the
point,will be adress will be
jumped to read here
-0x2-3: adress of everytime
the stack, the -0x4-5:adress of
adress will be the interrupt
read here handler, the
everytime adress will be
-0x4-5:adress of read here
the interrupt everytime
handler, the When an interrupt is raised, the cpu will allow acces
adress will be to r12-15 and push the resume adress to stack (in
read here order pc0 then pc1)
everytime
When an interrupt is raised, the cpu will allow acces instructions :
to r12-15 and push the resume adress to stack (in format:
order pc0 then pc1) rm,rn: general purpose registers
#imm:immediate signed 8bit value
instructions : *rm:memory at adress (pc+rm)
format: *#imm:memory at adress (pc+#imm)
rm,rn: general purpose registers sr: pr,ac
#imm:immediate signed 8bit value sr0-1: pr0-1/ac0-1, in/id
*rm:memory at adress (pc+rm) st: stack adress that is at 0x2,
*#imm:memory at adress (pc+#imm) abreviation for explanation only
sr: pr,ac nop :
sr0-1: pr0-1/ac0-1, in/id 0b0000000000000000
st: stack adress that is at 0x2, 0x0000
abreviation for explanation only No-OP:
nop : Does nothing
0b0000000000000000 1 clock
0x0000 mov rm,rn:
No-OP: 0b00100000mmmmnnnn
Does nothing 0x20mn
1 clock MOVe :
mov rm,rn: rm <- rn
0b00100000mmmmnnnn 1 clock
0x20mn mov rn,#imm:
MOVe : 0b1000nnnnmmmmmmmm
rm <- rn 0x8nmm
1 clock rn <- #imm
mov rn,#imm: 1 clock
0b1000nnnnmmmmmmmm mov rm,*rn:
0x8nmm 0b11000000mmmmnnnn
rn <- #imm 0xB0mn
1 clock rm <- *(pc+rn)
mov rm,*rn: 1 clock
0b11000000mmmmnnnn mov rn,*#imm:
0xB0mn 0b1001nnnnmmmmmmmm
rm <- *(pc+rn) 0x9nmm
1 clock rn <- *(pc+#imm)
mov rn,*#imm: 1 clock
0b1001nnnnmmmmmmmm mov *rm,rn:
0x9nmm 0b11000001mmmmnnnn
rn <- *(pc+#imm) 0xB1mn
1 clock *(pc+rm) <- rn
mov *rm,rn: 1 clock
0b11000001mmmmnnnn mov *#imm,rn:
0xB1mn 0b1010nnnnmmmmmmmm
*(pc+rm) <- rn 0xAnmm
1 clock *(pc+#imm) <- rn
mov *#imm,rn: 1 clock
0b1010nnnnmmmmmmmm mov *rm,*rn:
0xAnmm 0b11000010mmmmnnnn
*(pc+#imm) <- rn 0xB2mn
1 clock *(pc+rm) <- *(pc+rn)
mov *rm,*rn: 1 clock
0b11000010mmmmnnnn mmv rm, *sr:
0xB2mn 0b11000011mmmmssss
*(pc+rm) <- *(pc+rn) 0xB3ms
1 clock Memory MoVe
mmv rm, *sr: rm <- *sr
0b11000011mmmmssss Meant to be used with the accumulator
0xB3ms 1 clock
Memory MoVe mmv *sr, rm:
rm <- *sr 0b11000100ssssmmmm
Meant to be used with the accumulator 0xB4sm
1 clock *sr <- rm
mmv *sr, rm: Meant to be used with the accumulator
0b11000100ssssmmmm 1 clock
0xB4sm psh rm:
*sr <- rm 0b11000101mmmm0000
Meant to be used with the accumulator 0xB5m0
1 clock PuSH to stack:
psh rm: *(st+r11) <- rm
0b11000101mmmm0000 r11 <- r11+1
0xB5m0 2 clocks
PuSH to stack: pop rm:
*(st+r11) <- rm 0b11000110mmmm0000
r11 <- r11+1 0xB6m0
2 clocks POP from stack
pop rm: r11 <- r11-1
0b11000110mmmm0000 rm <- *(st+r11)
0xB6m0 2 clocks
POP from stack lds sr0-1,rm:
r11 <- r11-1 0b11100000ssssmmmm
rm <- *(st+r11) 0xE0sm
2 clocks LoaD Special :
lds sr0-1,rm: sr0-1 <- rm
0b11100000ssssmmmm nop on pc
0xE0sm 1 clock
LoaD Special : sts rm,sr0-1:
sr0-1 <- rm 0b11100001mmmmssss
nop on pc 0xE1ms
1 clock STore Special :
sts rm,sr0-1: rm <- sr0-1
0b11100001mmmmssss 1 clock
0xE1ms add rn,rm:
STore Special : 0b01000000nnnnmmmm
rm <- sr0-1 0x40nm
1 clock ADD :
add rn,rm: rn <- rn+rm
0b01000000nnnnmmmm 1 clock
0x40nm add r0,#imm:
ADD : 0b01001000mmmmmmmm
rn <- rn+rm 0x48mm
1 clock r0 <- r0+#imm
add r0,#imm: 1 clock
0b01001000mmmmmmmm sad sr0-1,rm:
0x48mm 0b11100010ssssmmmm
r0 <- r0+#imm 0xE2sm
1 clock Special ADd
sad sr0-1,rm: sr0-1 <- sr0-1+rm
0b11100010ssssmmmm (16bit add)
0xE2sm nop on pc
Special ADd 1 clock
sr0-1 <- sr0-1+rm sub rm,rn:
(16bit add) 0b01000001mmmmnnnn
nop on pc 0x41mn
1 clock SUBstract :
sub rm,rn: rm <- rm-rn
0b01000001mmmmnnnn 1 clock
0x41mn shl rm:
SUBstract : 0b01000010mmmm0000
rm <- rm-rn 0x42m0
1 clock SHift Left
shl rm: rm <- rm<<1
0b01000010mmmm0000 pure shift, no keep sign
0x42m0 1 clock
SHift Left shr rm:
rm <- rm<<1 0b01000011mmmm0000
pure shift, no keep sign 0x43m0
1 clock SHift Right
shr rm: rm <- rm>>1
0b01000011mmmm0000 pure shift, no keep sign
0x43m0 1 clock
SHift Right and rm,rn:
rm <- rm>>1 0b01000100mmmmnnnn
pure shift, no keep sign 0x44mn
1 clock binary AND :
and rm,rn: rm <- rm&rn
0b01000100mmmmnnnn 1 clock
0x44mn or rm,rn:
binary AND : 0b01000101mmmmnnnn
rm <- rm&rn 0x45mn
1 clock binary OR :
or rm,rn: rm <- rm|rn
0b01000101mmmmnnnn 1 clock
0x45mn xor rm,rn:
binary OR : 0b01000110mmmmnnnn
rm <- rm|rn 0x46mn
1 clock binary eXclusive OR:
xor rm,rn: rm <- rm^rn
0b01000110mmmmnnnn 1 clock
0x46mn not rm:
binary eXclusive OR: 0b01000111mmmmnnnn
rm <- rm^rn 0x47mn
1 clock binary NOT :
not rm: rm <- !rm
0b01000111mmmmnnnn binary not
0x47mn 1 clock
binary NOT : rtb :
rm <- !rm 0b0110000000000000
binary not 0x6000
1 clock Reset T Bit :
rtb : t <- 0
0b0110000000000000 1 clock
0x6000 gth rm,rn:
Reset T Bit : 0b01100001mmmmnnnn
t <- 0 0x61mn
1 clock Greater THan :
gth rm,rn: t <- rm > rn ? 1:0
0b01100001mmmmnnnn 1 clock
0x61mn gts rm,rn:
Greater THan : 0b01100100mmmmnnn
t <- rm > rn ? 1:0 0x64mn
1 clock Greater Than (Signed):
gts rm,rn: t <- rm > rn ? 1:0
0b01100100mmmmnnn (signed) (signed)
0x64mn 1 clock
Greater Than (Signed): eql rm,rn:
t <- rm > rn ? 1:0 0b01100010mmmmnnnn
(signed) (signed) 0x62mn
1 clock EQuaL :
eql rm,rn: t <- rm == rn ? 1:0
0b01100010mmmmnnnn 1 clock
0x62mn stb rm:
EQuaL : 0b01100011mmmm0000
t <- rm == rn ? 1:0 0x63m0
1 clock Store T Bit:
stb rm: rm <- t
0b01100011mmmm0000 1 clock
0x63m0 br *rm:
Store T Bit: 0b10110010mmmm0000
rm <- t 0x32m0
1 clock BRanch :
br *rm: pc <- pc + rm *2
0b10110010mmmm0000 (signed)
0x32m0 1 clock
BRanch : br *#imm:
pc <- pc + rm *2 0b10110000mmmmmmmm
(signed) 0x30mm
1 clock pc <- pc + #imm*2
br *#imm: 1 clock
0b10110000mmmmmmmm bt *rm:
0x30mm 0b10110101mmmm0000
pc <- pc + #imm*2 0x35m0
1 clock Branch if True:
bt *rm: If t == 1,
0b10110101mmmm0000 pc <- pc + rm *2
0x35m0 (signed)
Branch if True: else is nop
If t == 1, 1 clock
pc <- pc + rm *2 bt *#imm:
(signed) 0b10110001mmmmmmmm
else is nop 0x31mm
1 clock If t == 1,
bt *#imm: pc <- pc + #imm*2
0b10110001mmmmmmmm else is nop
0x31mm 1 clock
If t == 1, bf *rm:
pc <- pc + #imm*2 0b10110011mmmm0000
else is nop 0x33m0
1 clock Branch if False:
bf *rm: If t == 0,
0b10110011mmmm0000 pc <- pc + rm *2
0x33m0 (signed)
Branch if False: else is nop
If t == 0, 1 clock
pc <- pc + rm *2 jmp *sr:
(signed) 0b10110100ssss0000
else is nop 0x34s0
1 clock JuMP :
jmp *sr: pc <- sr
0b10110100ssss0000 nop on pc
0x34s0 2 clocks
JuMP : itp rm:
pc <- sr 0b01110001mmmm0000
nop on pc 0x71m0
2 clocks InTerruPt :
itp rm: Raises interrupt of id
0b01110001mmmm0000 rm
0x71m0 6 clocks
InTerruPt : dsi :
Raises interrupt of id 0b0111001000000000
rm 0x7200
6 clocks DiSable Interrupts:
dsi : Disables interrupts
0b0111001000000000 1 clock
0x7200 eni :
DiSable Interrupts: 0b0111001100000000
Disables interrupts 0x7300
1 clock ENable Interrupts:
eni : Enables interrupts
0b0111001100000000 1 clock
0x7300 rgi rm:
ENable Interrupts: 0b01110000mmmm0000
Enables interrupts 0x70m0
1 clock ReGister Interrupt :
rgi rm: rm should be as follows:
0b01110000mmmm0000 bit 0 : raisable by itp
0x70m0 bit 1 : raisable by bus
ReGister Interrupt : Sets rm to id on succes,
rm should be as follows: and 0xFF on failure
bit 0 : raisable by itp 2 clocks
bit 1 : raisable by bus
Sets rm to id on succes,
and 0xFF on failure
2 clocks