Update spec.txt
This commit is contained in:
Fcalva
parent
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commit
db7d68b317
1 changed files with 328 additions and 332 deletions
660
spec.txt
660
spec.txt
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@ -1,332 +1,328 @@
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instruction format:
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big endian
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16bits
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Bit order:
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0 : Largest (leftmost), 7 : smallest (rightmost)
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registers:
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r0-r12 (mov 0x0-0xc):
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general purpose
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8 bits
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r13-r15 (mov 0xd-0xf):
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Interrupt reserved
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8 bits
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ac,pr (special 0x0,1):
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accumulator, progam counter
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16bits
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ac0-1,pc0-1 (lds/sts 0x0-1,0x2-3):
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accumulator, progam counter
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8-8bits (lower-upper)
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id (special 0x2):
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interrupt data,
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set by the interrupt
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if raised by bus
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8bits
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in (Special 0x3):
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interrupt register,
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contains the type of
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interrupt
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4bits - bits 0-3 will always be 0
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t bit:
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is set by comp ops
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1bit
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calling conventions:
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r0-r1 : return registers
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r2-r11: call args
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r12 : stack pos
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r13-15:interrupt reserved (only adressable in interrupt mode)
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caller pushes desired return addr
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to stack, callee jumps to it
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Interrupts:
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Hardware interrupts:
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0x0 : Invalid instruction
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The 15 other interrupts are free to
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define by the user
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On interrupt (either called through
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the bus or itp)
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startup:
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the cpu will look
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at adress 0x0,and
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expects to find :
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-0x0-1: adress of
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the starting
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point,will be
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jumped to
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-0x2-3: adress of
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the stack, the
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adress will be
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read here
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everytime
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-0x4-5:adress of
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the interrupt
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handler, the
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adress will be
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read here
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everytime
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When an interrupt is raised, the cpu will allow acces
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to r12-15 and push the resume adress to stack (in
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order pc0 then pc1)
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instructions :
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format:
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rm,rn: general purpose registers
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#imm:immediate signed 8bit value
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*rm:memory at adress (pc+rm)
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*#imm:memory at adress (pc+#imm)
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sr: pr,ac
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sr0-1: pr0-1/ac0-1, in/id
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st: stack adress that is at 0x2,
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abreviation for explanation only
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nop :
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0b0000000000000000
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0x0000
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No-OP:
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Does nothing
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1 clock
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mov rm,rn:
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0b00100000mmmmnnnn
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0x20mn
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MOVe :
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rm <- rn
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1 clock
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mov rn,#imm:
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0b1000nnnnmmmmmmmm
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0x8nmm
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rn <- #imm
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1 clock
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mov rm,*rn:
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0b11000000mmmmnnnn
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0xB0mn
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rm <- *(pc+rn)
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1 clock
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mov rn,*#imm:
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0b1001nnnnmmmmmmmm
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0x9nmm
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rn <- *(pc+#imm)
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1 clock
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mov *rm,rn:
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0b11000001mmmmnnnn
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0xB1mn
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*(pc+rm) <- rn
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1 clock
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mov *#imm,rn:
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0b1010nnnnmmmmmmmm
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0xAnmm
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*(pc+#imm) <- rn
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1 clock
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mov *rm,*rn:
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0b11000010mmmmnnnn
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0xB2mn
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*(pc+rm) <- *(pc+rn)
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1 clock
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mmv rm, *sr:
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0b11000011mmmmssss
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0xB3ms
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Memory MoVe
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rm <- *sr
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Meant to be used with the accumulator
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1 clock
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mmv *sr, rm:
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0b11000100ssssmmmm
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0xB4sm
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*sr <- rm
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Meant to be used with the accumulator
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1 clock
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psh rm:
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0b11000101mmmm0000
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0xB5m0
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PuSH to stack:
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*(st+r11) <- rm
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r11 <- r11+1
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2 clocks
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pop rm:
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0b11000110mmmm0000
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0xB6m0
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POP from stack
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r11 <- r11-1
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rm <- *(st+r11)
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2 clocks
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lds sr0-1,rm:
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0b11100000ssssmmmm
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0xE0sm
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LoaD Special :
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sr0-1 <- rm
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nop on pc
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1 clock
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sts rm,sr0-1:
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0b11100001mmmmssss
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0xE1ms
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STore Special :
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rm <- sr0-1
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1 clock
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add rn,rm:
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0b01000000nnnnmmmm
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0x40nm
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ADD :
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rn <- rn+rm
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1 clock
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add r0,#imm:
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0b01001000mmmmmmmm
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0x48mm
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r0 <- r0+#imm
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1 clock
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sad sr0-1,rm:
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0b11100010ssssmmmm
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0xE2sm
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Special ADd
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sr0-1 <- sr0-1+rm
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(16bit add)
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nop on pc
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1 clock
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sub rm,rn:
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0b01000001mmmmnnnn
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0x41mn
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SUBstract :
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rm <- rm-rn
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1 clock
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shl rm:
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0b01000010mmmm0000
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0x42m0
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SHift Left
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rm <- rm<<1
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pure shift, no keep sign
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1 clock
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shr rm:
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0b01000011mmmm0000
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0x43m0
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SHift Right
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rm <- rm>>1
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pure shift, no keep sign
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1 clock
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and rm,rn:
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0b01000100mmmmnnnn
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0x44mn
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binary AND :
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rm <- rm&rn
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1 clock
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or rm,rn:
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0b01000101mmmmnnnn
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0x45mn
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binary OR :
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rm <- rm|rn
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1 clock
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xor rm,rn:
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0b01000110mmmmnnnn
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0x46mn
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binary eXclusive OR:
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rm <- rm^rn
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1 clock
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not rm:
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0b01000111mmmmnnnn
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0x47mn
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binary NOT :
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rm <- !rm
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binary not
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1 clock
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rtb :
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0b0110000000000000
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0x6000
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Reset T Bit :
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t <- 0
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1 clock
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gth rm,rn:
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0b01100001mmmmnnnn
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0x61mn
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Greater THan :
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t <- rm > rn ? 1:0
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1 clock
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gts rm,rn:
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0b01100100mmmmnnn
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0x64mn
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Greater Than (Signed):
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t <- rm > rn ? 1:0
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(signed) (signed)
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1 clock
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eql rm,rn:
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0b01100010mmmmnnnn
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0x62mn
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EQuaL :
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t <- rm == rn ? 1:0
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1 clock
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stb rm:
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0b01100011mmmm0000
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0x63m0
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Store T Bit:
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rm <- t
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1 clock
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br *rm:
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0b10110010mmmm0000
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0x32m0
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BRanch :
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pc <- pc + rm *2
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(signed)
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1 clock
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br *#imm:
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0b10110000mmmmmmmm
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0x30mm
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pc <- pc + #imm*2
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1 clock
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bt *rm:
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0b10110101mmmm0000
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0x35m0
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Branch if True:
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If t == 1,
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pc <- pc + rm *2
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(signed)
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else is nop
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1 clock
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bt *#imm:
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0b10110001mmmmmmmm
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0x31mm
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If t == 1,
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pc <- pc + #imm*2
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else is nop
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1 clock
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bf *rm:
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0b10110011mmmm0000
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0x33m0
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Branch if False:
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If t == 0,
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pc <- pc + rm *2
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(signed)
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else is nop
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1 clock
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jmp *sr:
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0b10110100ssss0000
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0x34s0
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JuMP :
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pc <- sr
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nop on pc
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2 clocks
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itp rm:
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0b01110001mmmm0000
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0x71m0
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InTerruPt :
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Raises interrupt of id
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rm
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6 clocks
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dsi :
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0b0111001000000000
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0x7200
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DiSable Interrupts:
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Disables interrupts
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1 clock
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eni :
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0b0111001100000000
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0x7300
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ENable Interrupts:
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Enables interrupts
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1 clock
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rgi rm:
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0b01110000mmmm0000
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0x70m0
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ReGister Interrupt :
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rm should be as follows:
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bit 0 : raisable by itp
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bit 1 : raisable by bus
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Sets rm to id on succes,
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and 0xFF on failure
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2 clocks
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instruction format:
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big endian
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16bits
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registers:
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r0-r12 (mov 0x0-0xc):
|
||||
general purpose
|
||||
8 bits
|
||||
r13-r15 (mov 0xd-0xf):
|
||||
Interrupt reserved
|
||||
8 bits
|
||||
ac,pr (special 0x0,1):
|
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accumulator, progam counter
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16bits
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ac0-1,pc0-1 (lds/sts 0x0-1,0x2-3):
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accumulator, progam counter
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8-8bits (lower-upper)
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id (special 0x2):
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interrupt data,
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set by the interrupt
|
||||
if raised by bus
|
||||
8bits
|
||||
in (Special 0x3):
|
||||
interrupt register,
|
||||
contains the type of
|
||||
interrupt
|
||||
4bits - bits 0-3 will always be 0
|
||||
t bit:
|
||||
is set by comp ops
|
||||
1bit
|
||||
calling conventions:
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||||
r0-r1 : return registers
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r2-r11: call args
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||||
r12 : stack pos
|
||||
r13-15:interrupt reserved (only adressable in interrupt mode)
|
||||
caller pushes desired return addr
|
||||
to stack, callee jumps to it
|
||||
|
||||
Interrupts:
|
||||
Hardware interrupts:
|
||||
0x0 : Invalid instruction
|
||||
The 15 other interrupts are free to
|
||||
define by the user
|
||||
On interrupt (either called through
|
||||
the bus or itp)
|
||||
startup:
|
||||
the cpu will look
|
||||
at adress 0x0,and
|
||||
expects to find :
|
||||
-0x0-1: adress of
|
||||
the starting
|
||||
point,will be
|
||||
jumped to
|
||||
-0x2-3: adress of
|
||||
the stack, the
|
||||
adress will be
|
||||
read here
|
||||
everytime
|
||||
-0x4-5:adress of
|
||||
the interrupt
|
||||
handler, the
|
||||
adress will be
|
||||
read here
|
||||
everytime
|
||||
When an interrupt is raised, the cpu will allow acces
|
||||
to r12-15 and push the resume adress to stack (in
|
||||
order pc0 then pc1)
|
||||
|
||||
instructions :
|
||||
format:
|
||||
rm,rn: general purpose registers
|
||||
#imm:immediate signed 8bit value
|
||||
*rm:memory at adress (pc+rm)
|
||||
*#imm:memory at adress (pc+#imm)
|
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sr: pr,ac
|
||||
sr0-1: pr0-1/ac0-1, in/id
|
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st: stack adress that is at 0x2,
|
||||
abreviation for explanation only
|
||||
nop :
|
||||
0b0000000000000000
|
||||
0x0000
|
||||
No-OP:
|
||||
Does nothing
|
||||
1 clock
|
||||
mov rm,rn:
|
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0b00100000mmmmnnnn
|
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0x20mn
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MOVe :
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rm <- rn
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1 clock
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mov rn,#imm:
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0b1000nnnnmmmmmmmm
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0x8nmm
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rn <- #imm
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1 clock
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mov rm,*rn:
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0b11000000mmmmnnnn
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0xB0mn
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rm <- *(pc+rn)
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1 clock
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mov rn,*#imm:
|
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0b1001nnnnmmmmmmmm
|
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0x9nmm
|
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rn <- *(pc+#imm)
|
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1 clock
|
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mov *rm,rn:
|
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0b11000001mmmmnnnn
|
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0xB1mn
|
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*(pc+rm) <- rn
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1 clock
|
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mov *#imm,rn:
|
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0b1010nnnnmmmmmmmm
|
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0xAnmm
|
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*(pc+#imm) <- rn
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1 clock
|
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mov *rm,*rn:
|
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0b11000010mmmmnnnn
|
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0xB2mn
|
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*(pc+rm) <- *(pc+rn)
|
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1 clock
|
||||
mmv rm, *sr:
|
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0b11000011mmmmssss
|
||||
0xB3ms
|
||||
Memory MoVe
|
||||
rm <- *sr
|
||||
Meant to be used with the accumulator
|
||||
1 clock
|
||||
mmv *sr, rm:
|
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0b11000100ssssmmmm
|
||||
0xB4sm
|
||||
*sr <- rm
|
||||
Meant to be used with the accumulator
|
||||
1 clock
|
||||
psh rm:
|
||||
0b11000101mmmm0000
|
||||
0xB5m0
|
||||
PuSH to stack:
|
||||
*(st+r11) <- rm
|
||||
r11 <- r11+1
|
||||
2 clocks
|
||||
pop rm:
|
||||
0b11000110mmmm0000
|
||||
0xB6m0
|
||||
POP from stack
|
||||
r11 <- r11-1
|
||||
rm <- *(st+r11)
|
||||
2 clocks
|
||||
lds sr0-1,rm:
|
||||
0b11100000ssssmmmm
|
||||
0xE0sm
|
||||
LoaD Special :
|
||||
sr0-1 <- rm
|
||||
nop on pc
|
||||
1 clock
|
||||
sts rm,sr0-1:
|
||||
0b11100001mmmmssss
|
||||
0xE1ms
|
||||
STore Special :
|
||||
rm <- sr0-1
|
||||
1 clock
|
||||
add rn,rm:
|
||||
0b01000000nnnnmmmm
|
||||
0x40nm
|
||||
ADD :
|
||||
rn <- rn+rm
|
||||
1 clock
|
||||
add r0,#imm:
|
||||
0b01001000mmmmmmmm
|
||||
0x48mm
|
||||
r0 <- r0+#imm
|
||||
1 clock
|
||||
sad sr0-1,rm:
|
||||
0b11100010ssssmmmm
|
||||
0xE2sm
|
||||
Special ADd
|
||||
sr0-1 <- sr0-1+rm
|
||||
(16bit add)
|
||||
nop on pc
|
||||
1 clock
|
||||
sub rm,rn:
|
||||
0b01000001mmmmnnnn
|
||||
0x41mn
|
||||
SUBstract :
|
||||
rm <- rm-rn
|
||||
1 clock
|
||||
shl rm:
|
||||
0b01000010mmmm0000
|
||||
0x42m0
|
||||
SHift Left
|
||||
rm <- rm<<1
|
||||
pure shift, no keep sign
|
||||
1 clock
|
||||
shr rm:
|
||||
0b01000011mmmm0000
|
||||
0x43m0
|
||||
SHift Right
|
||||
rm <- rm>>1
|
||||
pure shift, no keep sign
|
||||
1 clock
|
||||
and rm,rn:
|
||||
0b01000100mmmmnnnn
|
||||
0x44mn
|
||||
binary AND :
|
||||
rm <- rm&rn
|
||||
1 clock
|
||||
or rm,rn:
|
||||
0b01000101mmmmnnnn
|
||||
0x45mn
|
||||
binary OR :
|
||||
rm <- rm|rn
|
||||
1 clock
|
||||
xor rm,rn:
|
||||
0b01000110mmmmnnnn
|
||||
0x46mn
|
||||
binary eXclusive OR:
|
||||
rm <- rm^rn
|
||||
1 clock
|
||||
not rm:
|
||||
0b01000111mmmmnnnn
|
||||
0x47mn
|
||||
binary NOT :
|
||||
rm <- !rm
|
||||
binary not
|
||||
1 clock
|
||||
rtb :
|
||||
0b0110000000000000
|
||||
0x6000
|
||||
Reset T Bit :
|
||||
t <- 0
|
||||
1 clock
|
||||
gth rm,rn:
|
||||
0b01100001mmmmnnnn
|
||||
0x61mn
|
||||
Greater THan :
|
||||
t <- rm > rn ? 1:0
|
||||
1 clock
|
||||
gts rm,rn:
|
||||
0b01100100mmmmnnn
|
||||
0x64mn
|
||||
Greater Than (Signed):
|
||||
t <- rm > rn ? 1:0
|
||||
(signed) (signed)
|
||||
1 clock
|
||||
eql rm,rn:
|
||||
0b01100010mmmmnnnn
|
||||
0x62mn
|
||||
EQuaL :
|
||||
t <- rm == rn ? 1:0
|
||||
1 clock
|
||||
stb rm:
|
||||
0b01100011mmmm0000
|
||||
0x63m0
|
||||
Store T Bit:
|
||||
rm <- t
|
||||
1 clock
|
||||
br *rm:
|
||||
0b10110010mmmm0000
|
||||
0x32m0
|
||||
BRanch :
|
||||
pc <- pc + rm *2
|
||||
(signed)
|
||||
1 clock
|
||||
br *#imm:
|
||||
0b10110000mmmmmmmm
|
||||
0x30mm
|
||||
pc <- pc + #imm*2
|
||||
1 clock
|
||||
bt *rm:
|
||||
0b10110101mmmm0000
|
||||
0x35m0
|
||||
Branch if True:
|
||||
If t == 1,
|
||||
pc <- pc + rm *2
|
||||
(signed)
|
||||
else is nop
|
||||
1 clock
|
||||
bt *#imm:
|
||||
0b10110001mmmmmmmm
|
||||
0x31mm
|
||||
If t == 1,
|
||||
pc <- pc + #imm*2
|
||||
else is nop
|
||||
1 clock
|
||||
bf *rm:
|
||||
0b10110011mmmm0000
|
||||
0x33m0
|
||||
Branch if False:
|
||||
If t == 0,
|
||||
pc <- pc + rm *2
|
||||
(signed)
|
||||
else is nop
|
||||
1 clock
|
||||
jmp *sr:
|
||||
0b10110100ssss0000
|
||||
0x34s0
|
||||
JuMP :
|
||||
pc <- sr
|
||||
nop on pc
|
||||
2 clocks
|
||||
itp rm:
|
||||
0b01110001mmmm0000
|
||||
0x71m0
|
||||
InTerruPt :
|
||||
Raises interrupt of id
|
||||
rm
|
||||
6 clocks
|
||||
dsi :
|
||||
0b0111001000000000
|
||||
0x7200
|
||||
DiSable Interrupts:
|
||||
Disables interrupts
|
||||
1 clock
|
||||
eni :
|
||||
0b0111001100000000
|
||||
0x7300
|
||||
ENable Interrupts:
|
||||
Enables interrupts
|
||||
1 clock
|
||||
rgi rm:
|
||||
0b01110000mmmm0000
|
||||
0x70m0
|
||||
ReGister Interrupt :
|
||||
rm should be as follows:
|
||||
bit 0 : raisable by itp
|
||||
bit 1 : raisable by bus
|
||||
Sets rm to id on succes,
|
||||
and 0xFF on failure
|
||||
2 clocks
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue