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cpg: fix incorrect access size to SDMR3_CL2 and SDMR3_CL3

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Lephenixnoir 2025-03-11 15:32:37 +01:00 • committed by Chen-Zhanming
parent 66f173bd11
commit 302aeb5cdf
1 changed files with 2 additions and 2 deletions
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4
src/cpg/overclock.c
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@ -21,8 +21,8 @@
// Low-level clock speed access
//---
#define SH7305_SDMR3_CL2 ((volatile uint8_t *)0xFEC15040)
#define SH7305_SDMR3_CL3 ((volatile uint8_t *)0xFEC15060)
#define SH7305_SDMR3_CL2 ((volatile uint16_t *)0xFEC15040)
#define SH7305_SDMR3_CL3 ((volatile uint16_t *)0xFEC15060)
//---
// Predefined clock speeds